llvm/llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir

# RUN: llc --verify-machineinstrs -mtriple=aarch64 -mcpu=neoverse-n1 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -debug-only=pipeliner 2>&1 | FileCheck %s
# REQUIRES: asserts

# Check that instructions referencing NZCV are not pipelined

# CHECK: SU([[SU0:[0-9]+]]):   nofpexcept FCMPSri {{.*}}, implicit-def $nzcv, implicit $fpcr
# CHECK: SU([[SU1:[0-9]+]]):   {{.*}} = FCSELSrrr {{.*}}, {{.*}}, 1, implicit $nzcv
# CHECK: Do not pipeline SU([[SU0:[0-9]+]])
# CHECK: Do not pipeline SU([[SU1:[0-9]+]])

--- |
  define dso_local void @KERNEL(ptr noalias nocapture noundef writeonly %a, ptr nocapture noundef readonly %b, i32 noundef %n) local_unnamed_addr #0 {
  entry:
    %cmp19 = icmp sgt i32 %n, 0
    br i1 %cmp19, label %for.body.preheader, label %for.cond.cleanup

  for.body.preheader:                               ; preds = %entry
    %wide.trip.count = zext nneg i32 %n to i64
    br label %for.body

  for.cond.cleanup:                                 ; preds = %for.body, %entry
    ret void

  for.body:                                         ; preds = %for.body.preheader, %for.body
    %lsr.iv24 = phi i64 [ %wide.trip.count, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
    %lsr.iv22 = phi ptr [ %b, %for.body.preheader ], [ %scevgep23, %for.body ]
    %lsr.iv = phi ptr [ %a, %for.body.preheader ], [ %scevgep, %for.body ]
    %0 = load float, ptr %lsr.iv22, align 4
    %tobool = fcmp une float %0, 0.000000e+00
    %. = select i1 %tobool, float 1.000000e+00, float 2.000000e+00
    %add = fadd float %0, %.
    store float %add, ptr %lsr.iv, align 4
    %scevgep = getelementptr i8, ptr %lsr.iv, i64 4
    %scevgep23 = getelementptr i8, ptr %lsr.iv22, i64 4
    %lsr.iv.next = add nsw i64 %lsr.iv24, -1
    %exitcond.not = icmp eq i64 %lsr.iv.next, 0
    br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
  }

...
---
name:            KERNEL
tracksRegLiveness: true
liveins:
  - { reg: '$x0', virtual-reg: '%7' }
  - { reg: '$x1', virtual-reg: '%8' }
  - { reg: '$w2', virtual-reg: '%9' }
body:             |
  bb.0.entry:
    successors: %bb.1(0x50000000), %bb.2(0x30000000)
    liveins: $x0, $x1, $w2

    %9:gpr32common = COPY $w2
    %8:gpr64 = COPY $x1
    %7:gpr64 = COPY $x0
    dead $wzr = SUBSWri %9, 1, 0, implicit-def $nzcv
    Bcc 11, %bb.2, implicit $nzcv
    B %bb.1

  bb.1.for.body.preheader:
    %11:gpr32 = ORRWrs $wzr, %9, 0
    %0:gpr64all = SUBREG_TO_REG 0, killed %11, %subreg.sub_32
    %14:fpr32 = FMOVSi 0
    %15:fpr32 = FMOVSi 112
    B %bb.3

  bb.2.for.cond.cleanup:
    RET_ReallyLR

  bb.3.for.body:
    successors: %bb.2(0x04000000), %bb.3(0x7c000000)

    %1:gpr64sp = PHI %0, %bb.1, %6, %bb.3
    %2:gpr64sp = PHI %8, %bb.1, %5, %bb.3
    %3:gpr64sp = PHI %7, %bb.1, %4, %bb.3
    early-clobber %12:gpr64sp, %13:fpr32 = LDRSpost %2, 4 :: (load (s32) from %ir.lsr.iv22)
    nofpexcept FCMPSri %13, implicit-def $nzcv, implicit $fpcr
    %16:fpr32 = FCSELSrrr %15, %14, 1, implicit $nzcv
    %17:fpr32 = nofpexcept FADDSrr %13, killed %16, implicit $fpcr
    early-clobber %18:gpr64sp = STRSpost killed %17, %3, 4 :: (store (s32) into %ir.lsr.iv)
    %4:gpr64all = COPY %18
    %5:gpr64all = COPY %12
    %19:gpr64 = nsw SUBSXri %1, 1, 0, implicit-def $nzcv
    %6:gpr64all = COPY %19
    Bcc 0, %bb.2, implicit $nzcv
    B %bb.3

...