# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=machine-combiner -o - -simplify-mir -mtriple=aarch64-unknown-linux-gnu -mattr=+fullfp16 -verify-machineinstrs %s | FileCheck %s
--- |
; ModuleID = 'lit.ll'
source_filename = "lit.ll"
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-gnu"
define void @indexed_2s(<2 x float> %shuf, <2 x float> %mu, <2 x float> %ad, ptr %ret) #0 {
entry:
%shuffle = shufflevector <2 x float> %shuf, <2 x float> undef, <2 x i32> zeroinitializer
br label %for.cond
for.cond: ; preds = %for.cond, %entry
%mul = fmul <2 x float> %mu, %shuffle
%add = fadd <2 x float> %mul, %ad
store <2 x float> %add, ptr %ret, align 16
br label %for.cond
}
define void @indexed_2s_rev(<2 x float> %shuf, <2 x float> %mu, <2 x float> %ad, ptr %ret) #0 {
entry:
%shuffle = shufflevector <2 x float> %shuf, <2 x float> undef, <2 x i32> zeroinitializer
br label %for.cond
for.cond: ; preds = %for.cond, %entry
%mul = fmul <2 x float> %shuffle, %mu
%add = fadd <2 x float> %mul, %ad
store <2 x float> %add, ptr %ret, align 16
br label %for.cond
}
define void @indexed_2d(<2 x double> %shuf, <2 x double> %mu, <2 x double> %ad, ptr %ret) #0 {
entry:
%shuffle = shufflevector <2 x double> %shuf, <2 x double> undef, <2 x i32> zeroinitializer
br label %for.cond
for.cond: ; preds = %for.cond, %entry
%mul = fmul <2 x double> %mu, %shuffle
%add = fadd <2 x double> %mul, %ad
store <2 x double> %add, ptr %ret, align 16
br label %for.cond
}
define void @indexed_4s(<4 x float> %shuf, <4 x float> %mu, <4 x float> %ad, ptr %ret) #0 {
entry:
%shuffle = shufflevector <4 x float> %shuf, <4 x float> undef, <4 x i32> zeroinitializer
br label %for.cond
for.cond: ; preds = %for.cond, %entry
%mul = fmul <4 x float> %mu, %shuffle
%add = fadd <4 x float> %mul, %ad
store <4 x float> %add, ptr %ret, align 16
br label %for.cond
}
define void @indexed_4h(<4 x half> %shuf, <4 x half> %mu, <4 x half> %ad, ptr %ret) #0 {
entry:
%shuffle = shufflevector <4 x half> %shuf, <4 x half> undef, <4 x i32> zeroinitializer
br label %for.cond
for.cond:
%mul = fmul <4 x half> %mu, %shuffle
%add = fadd <4 x half> %mul, %ad
store <4 x half> %add, ptr %ret, align 16
br label %for.cond
}
define void @indexed_8h(<8 x half> %shuf, <8 x half> %mu, <8 x half> %ad, ptr %ret) #0 {
entry:
%shuffle = shufflevector <8 x half> %shuf, <8 x half> undef, <8 x i32> zeroinitializer
br label %for.cond
for.cond:
%mul = fmul <8 x half> %mu, %shuffle
%add = fadd <8 x half> %mul, %ad
store <8 x half> %add, ptr %ret, align 16
br label %for.cond
}
define void @kill_state(<2 x float> %shuf, <2 x float> %mu, <2 x float> %ad,
ptr %ret, ptr %ret2, float %f) #0 {
entry:
%zero_elem = extractelement <2 x float> %shuf, i32 0
%ins = insertelement <2 x float> undef, float %zero_elem, i32 0
%shuffle = shufflevector <2 x float> %ins, <2 x float> undef, <2 x i32> zeroinitializer
%ins2 = insertelement <2 x float> %ins, float %f, i32 1
store <2 x float> %ins2, ptr %ret2, align 8
br label %for.cond
for.cond: ; preds = %for.cond, %entry
%mul = fmul <2 x float> %mu, %shuffle
%add = fadd <2 x float> %mul, %ad
store <2 x float> %add, ptr %ret, align 16
br label %for.cond
}
define void @extracopy(<2 x float> %shuf, <2 x float> %mu, <2 x float> %ad, ptr %ret) #0 {
unreachable
}
attributes #0 = { "target-cpu"="cortex-a57" }
...
---
name: indexed_2s
alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: fpr64 }
- { id: 1, class: fpr64 }
- { id: 2, class: fpr64 }
- { id: 3, class: fpr64 }
- { id: 4, class: gpr64common }
- { id: 5, class: fpr64 }
- { id: 6, class: fpr64 }
- { id: 7, class: fpr128 }
- { id: 8, class: fpr128 }
- { id: 9, class: fpr64 }
- { id: 10, class: fpr64 }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
- { reg: '$d2', virtual-reg: '%3' }
- { reg: '$x0', virtual-reg: '%4' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: indexed_2s
; CHECK: bb.0.entry:
; CHECK-NEXT: liveins: $d0, $d1, $d2, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d2
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub
; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr64 = COPY [[COPY1]]
; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr64 = COPY [[COPY2]]
; CHECK-NEXT: [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.for.cond:
; CHECK-NEXT: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY5]], [[INSERT_SUBREG]], 0, implicit $fpcr
; CHECK-NEXT: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY4]], implicit $fpcr
; CHECK-NEXT: STRDui killed [[FADDv2f32_]], [[COPY]], 0 :: (store (s64) into %ir.ret, align 16)
; CHECK-NEXT: B %bb.1
bb.0.entry:
liveins: $d0, $d1, $d2, $x0
%4:gpr64common = COPY $x0
%3:fpr64 = COPY $d2
%2:fpr64 = COPY $d1
%1:fpr64 = COPY $d0
%8:fpr128 = IMPLICIT_DEF
%7:fpr128 = INSERT_SUBREG %8, %1, %subreg.dsub
%6:fpr64 = COPY %3
%5:fpr64 = COPY %2
%0:fpr64 = DUPv2i32lane killed %7, 0
bb.1.for.cond:
%9:fpr64 = FMULv2f32 %5, %0, implicit $fpcr
%10:fpr64 = FADDv2f32 killed %9, %6, implicit $fpcr
STRDui killed %10, %4, 0 :: (store 8 into %ir.ret, align 16)
B %bb.1
...
---
name: indexed_2s_rev
alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: fpr64 }
- { id: 1, class: fpr64 }
- { id: 2, class: fpr64 }
- { id: 3, class: fpr64 }
- { id: 4, class: gpr64common }
- { id: 5, class: fpr64 }
- { id: 6, class: fpr64 }
- { id: 7, class: fpr128 }
- { id: 8, class: fpr128 }
- { id: 9, class: fpr64 }
- { id: 10, class: fpr64 }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
- { reg: '$d2', virtual-reg: '%3' }
- { reg: '$x0', virtual-reg: '%4' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: indexed_2s_rev
; CHECK: bb.0.entry:
; CHECK-NEXT: liveins: $d0, $d1, $d2, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d2
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub
; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr64 = COPY [[COPY1]]
; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr64 = COPY [[COPY2]]
; CHECK-NEXT: [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.for.cond:
; CHECK-NEXT: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY5]], [[INSERT_SUBREG]], 0, implicit $fpcr
; CHECK-NEXT: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY4]], implicit $fpcr
; CHECK-NEXT: STRDui killed [[FADDv2f32_]], [[COPY]], 0 :: (store (s64) into %ir.ret, align 16)
; CHECK-NEXT: B %bb.1
bb.0.entry:
liveins: $d0, $d1, $d2, $x0
%4:gpr64common = COPY $x0
%3:fpr64 = COPY $d2
%2:fpr64 = COPY $d1
%1:fpr64 = COPY $d0
%8:fpr128 = IMPLICIT_DEF
%7:fpr128 = INSERT_SUBREG %8, %1, %subreg.dsub
%6:fpr64 = COPY %3
%5:fpr64 = COPY %2
%0:fpr64 = DUPv2i32lane killed %7, 0
bb.1.for.cond:
%9:fpr64 = FMULv2f32 %0, %5, implicit $fpcr
%10:fpr64 = FADDv2f32 killed %9, %6, implicit $fpcr
STRDui killed %10, %4, 0 :: (store 8 into %ir.ret, align 16)
B %bb.1
...
---
name: indexed_2d
alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: fpr128 }
- { id: 1, class: fpr128 }
- { id: 2, class: fpr128 }
- { id: 3, class: fpr128 }
- { id: 4, class: gpr64common }
- { id: 5, class: fpr128 }
- { id: 6, class: fpr128 }
- { id: 7, class: fpr128 }
- { id: 8, class: fpr128 }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
- { reg: '$q2', virtual-reg: '%3' }
- { reg: '$x0', virtual-reg: '%4' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: indexed_2d
; CHECK: bb.0.entry:
; CHECK-NEXT: liveins: $q0, $q1, $q2, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q2
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q1
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr128 = COPY [[COPY1]]
; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr128 = COPY [[COPY2]]
; CHECK-NEXT: [[DUPv2i64lane:%[0-9]+]]:fpr128 = DUPv2i64lane [[COPY3]], 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.for.cond:
; CHECK-NEXT: [[FMULv2i64_indexed:%[0-9]+]]:fpr128 = FMULv2i64_indexed [[COPY5]], [[COPY3]], 0, implicit $fpcr
; CHECK-NEXT: [[FADDv2f64_:%[0-9]+]]:fpr128 = FADDv2f64 killed [[FMULv2i64_indexed]], [[COPY4]], implicit $fpcr
; CHECK-NEXT: STRQui killed [[FADDv2f64_]], [[COPY]], 0 :: (store (s128) into %ir.ret)
; CHECK-NEXT: B %bb.1
bb.0.entry:
liveins: $q0, $q1, $q2, $x0
%4:gpr64common = COPY $x0
%3:fpr128 = COPY $q2
%2:fpr128 = COPY $q1
%1:fpr128 = COPY $q0
%6:fpr128 = COPY %3
%5:fpr128 = COPY %2
%0:fpr128 = DUPv2i64lane %1, 0
bb.1.for.cond:
%7:fpr128 = FMULv2f64 %5, %0, implicit $fpcr
%8:fpr128 = FADDv2f64 killed %7, %6, implicit $fpcr
STRQui killed %8, %4, 0 :: (store 16 into %ir.ret)
B %bb.1
...
---
name: indexed_4s
alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: fpr128 }
- { id: 1, class: fpr128 }
- { id: 2, class: fpr128 }
- { id: 3, class: fpr128 }
- { id: 4, class: gpr64common }
- { id: 5, class: fpr128 }
- { id: 6, class: fpr128 }
- { id: 7, class: fpr128 }
- { id: 8, class: fpr128 }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
- { reg: '$q2', virtual-reg: '%3' }
- { reg: '$x0', virtual-reg: '%4' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: indexed_4s
; CHECK: bb.0.entry:
; CHECK-NEXT: liveins: $q0, $q1, $q2, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q2
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q1
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr128 = COPY [[COPY1]]
; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr128 = COPY [[COPY2]]
; CHECK-NEXT: [[DUPv4i32lane:%[0-9]+]]:fpr128 = DUPv4i32lane [[COPY3]], 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.for.cond:
; CHECK-NEXT: [[FMULv4i32_indexed:%[0-9]+]]:fpr128 = FMULv4i32_indexed [[COPY5]], [[COPY3]], 0, implicit $fpcr
; CHECK-NEXT: [[FADDv4f32_:%[0-9]+]]:fpr128 = FADDv4f32 killed [[FMULv4i32_indexed]], [[COPY4]], implicit $fpcr
; CHECK-NEXT: STRQui killed [[FADDv4f32_]], [[COPY]], 0 :: (store (s128) into %ir.ret)
; CHECK-NEXT: B %bb.1
bb.0.entry:
liveins: $q0, $q1, $q2, $x0
%4:gpr64common = COPY $x0
%3:fpr128 = COPY $q2
%2:fpr128 = COPY $q1
%1:fpr128 = COPY $q0
%6:fpr128 = COPY %3
%5:fpr128 = COPY %2
%0:fpr128 = DUPv4i32lane %1, 0
bb.1.for.cond:
%7:fpr128 = FMULv4f32 %5, %0, implicit $fpcr
%8:fpr128 = FADDv4f32 killed %7, %6, implicit $fpcr
STRQui killed %8, %4, 0 :: (store 16 into %ir.ret)
B %bb.1
...
---
name: indexed_4h
alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: fpr64 }
- { id: 1, class: fpr64 }
- { id: 2, class: fpr64 }
- { id: 3, class: fpr64 }
- { id: 4, class: gpr64common }
- { id: 5, class: fpr128 }
- { id: 6, class: fpr128 }
- { id: 7, class: fpr64 }
- { id: 8, class: fpr64 }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
- { reg: '$d2', virtual-reg: '%3' }
- { reg: '$x0', virtual-reg: '%4' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: indexed_4h
; CHECK: bb.0.entry:
; CHECK-NEXT: liveins: $d0, $d1, $d2, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d2
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128_lo = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub
; CHECK-NEXT: [[DUPv4i16lane:%[0-9]+]]:fpr64 = DUPv4i16lane [[INSERT_SUBREG]], 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.for.cond:
; CHECK-NEXT: [[FMULv4i16_indexed:%[0-9]+]]:fpr64 = FMULv4i16_indexed [[COPY2]], [[INSERT_SUBREG]], 0, implicit $fpcr
; CHECK-NEXT: [[FADDv4f16_:%[0-9]+]]:fpr64 = FADDv4f16 killed [[FMULv4i16_indexed]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: STRDui killed [[FADDv4f16_]], [[COPY]], 0 :: (store (s64) into %ir.ret, align 16)
; CHECK-NEXT: B %bb.1
bb.0.entry:
liveins: $d0, $d1, $d2, $x0
%4:gpr64common = COPY $x0
%3:fpr64 = COPY $d2
%2:fpr64 = COPY $d1
%1:fpr64 = COPY $d0
%6:fpr128 = IMPLICIT_DEF
%5:fpr128 = INSERT_SUBREG %6, %1, %subreg.dsub
%0:fpr64 = DUPv4i16lane killed %5, 0
bb.1.for.cond:
%7:fpr64 = FMULv4f16 %2, %0, implicit $fpcr
%8:fpr64 = FADDv4f16 killed %7, %3, implicit $fpcr
STRDui killed %8, %4, 0 :: (store 8 into %ir.ret, align 16)
B %bb.1
...
---
name: indexed_8h
alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: fpr128 }
- { id: 1, class: fpr128 }
- { id: 2, class: fpr128 }
- { id: 3, class: fpr128 }
- { id: 4, class: gpr64common }
- { id: 5, class: fpr128 }
- { id: 6, class: fpr128 }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
- { reg: '$q2', virtual-reg: '%3' }
- { reg: '$x0', virtual-reg: '%4' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: indexed_8h
; CHECK: bb.0.entry:
; CHECK-NEXT: liveins: $q0, $q1, $q2, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q2
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q1
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr128_lo = COPY $q0
; CHECK-NEXT: [[DUPv8i16lane:%[0-9]+]]:fpr128 = DUPv8i16lane [[COPY3]], 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.for.cond:
; CHECK-NEXT: [[FMULv8i16_indexed:%[0-9]+]]:fpr128 = FMULv8i16_indexed [[COPY2]], [[COPY3]], 0, implicit $fpcr
; CHECK-NEXT: [[FADDv8f16_:%[0-9]+]]:fpr128 = FADDv8f16 killed [[FMULv8i16_indexed]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: STRQui killed [[FADDv8f16_]], [[COPY]], 0 :: (store (s128) into %ir.ret)
; CHECK-NEXT: B %bb.1
bb.0.entry:
liveins: $q0, $q1, $q2, $x0
%4:gpr64common = COPY $x0
%3:fpr128 = COPY $q2
%2:fpr128 = COPY $q1
%1:fpr128 = COPY $q0
%0:fpr128 = DUPv8i16lane %1, 0
bb.1.for.cond:
%5:fpr128 = FMULv8f16 %2, %0, implicit $fpcr
%6:fpr128 = FADDv8f16 killed %5, %3, implicit $fpcr
STRQui killed %6, %4, 0 :: (store 16 into %ir.ret)
B %bb.1
...
---
name: kill_state
alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: fpr64 }
- { id: 1, class: fpr64 }
- { id: 2, class: fpr64 }
- { id: 3, class: fpr64 }
- { id: 4, class: gpr64common }
- { id: 5, class: gpr64common }
- { id: 6, class: fpr32 }
- { id: 7, class: fpr64 }
- { id: 8, class: fpr64 }
- { id: 9, class: fpr128 }
- { id: 10, class: fpr128 }
- { id: 11, class: fpr128 }
- { id: 12, class: fpr128 }
- { id: 13, class: fpr128 }
- { id: 14, class: fpr64 }
- { id: 15, class: fpr64 }
- { id: 16, class: fpr64 }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
- { reg: '$d2', virtual-reg: '%3' }
- { reg: '$x0', virtual-reg: '%4' }
- { reg: '$x1', virtual-reg: '%5' }
- { reg: '$s3', virtual-reg: '%6' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: kill_state
; CHECK: bb.0.entry:
; CHECK-NEXT: liveins: $d0, $d1, $d2, $x0, $x1, $s3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64common = COPY $x0
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $d2
; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY5]], %subreg.dsub
; CHECK-NEXT: [[COPY6:%[0-9]+]]:fpr64 = COPY [[COPY3]]
; CHECK-NEXT: [[COPY7:%[0-9]+]]:fpr64 = COPY [[COPY4]]
; CHECK-NEXT: [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.ssub
; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, killed [[INSERT_SUBREG1]], 0
; CHECK-NEXT: [[COPY8:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub
; CHECK-NEXT: STRDui killed [[COPY8]], [[COPY1]], 0 :: (store (s64) into %ir.ret2)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.for.cond:
; CHECK-NEXT: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY7]], [[INSERT_SUBREG]], 0, implicit $fpcr
; CHECK-NEXT: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY6]], implicit $fpcr
; CHECK-NEXT: STRDui killed [[FADDv2f32_]], [[COPY2]], 0 :: (store (s64) into %ir.ret, align 16)
; CHECK-NEXT: B %bb.1
bb.0.entry:
liveins: $d0, $d1, $d2, $x0, $x1, $s3
%6:fpr32 = COPY $s3
%5:gpr64common = COPY $x1
%4:gpr64common = COPY $x0
%3:fpr64 = COPY $d2
%2:fpr64 = COPY $d1
%1:fpr64 = COPY $d0
%10:fpr128 = IMPLICIT_DEF
%9:fpr128 = INSERT_SUBREG %10, %1, %subreg.dsub
%8:fpr64 = COPY %3
%7:fpr64 = COPY %2
%0:fpr64 = DUPv2i32lane %9, 0
%12:fpr128 = IMPLICIT_DEF
%11:fpr128 = INSERT_SUBREG %12, %6, %subreg.ssub
%13:fpr128 = INSvi32lane killed %9, 1, killed %11, 0
%14:fpr64 = COPY %13.dsub
STRDui killed %14, %5, 0 :: (store (s64) into %ir.ret2)
bb.1.for.cond:
%15:fpr64 = FMULv2f32 %7, %0, implicit $fpcr
%16:fpr64 = FADDv2f32 killed %15, %8, implicit $fpcr
STRDui killed %16, %4, 0 :: (store (s64) into %ir.ret, align 16)
B %bb.1
...
---
name: extracopy
alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: fpr64 }
- { id: 1, class: fpr64 }
- { id: 2, class: fpr64 }
- { id: 3, class: fpr64 }
- { id: 4, class: gpr64common }
- { id: 5, class: fpr64 }
- { id: 6, class: fpr64 }
- { id: 7, class: fpr128 }
- { id: 8, class: fpr128 }
- { id: 9, class: fpr64 }
- { id: 10, class: fpr64 }
- { id: 11, class: fpr64 }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
- { reg: '$d2', virtual-reg: '%3' }
- { reg: '$x0', virtual-reg: '%4' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: extracopy
; CHECK: bb.0:
; CHECK-NEXT: liveins: $d0, $d1, $d2, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d2
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub
; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr64 = COPY [[COPY1]]
; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr64 = COPY [[COPY2]]
; CHECK-NEXT: [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
; CHECK-NEXT: [[COPY6:%[0-9]+]]:fpr64 = COPY [[DUPv2i32lane]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY5]], [[INSERT_SUBREG]], 0, implicit $fpcr
; CHECK-NEXT: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY4]], implicit $fpcr
; CHECK-NEXT: STRDui killed [[FADDv2f32_]], [[COPY]], 0 :: (store (s64), align 16)
; CHECK-NEXT: B %bb.1
bb.0:
liveins: $d0, $d1, $d2, $x0
%4:gpr64common = COPY $x0
%3:fpr64 = COPY $d2
%2:fpr64 = COPY $d1
%1:fpr64 = COPY $d0
%8:fpr128 = IMPLICIT_DEF
%7:fpr128 = INSERT_SUBREG %8, %1, %subreg.dsub
%6:fpr64 = COPY %3
%5:fpr64 = COPY %2
%11:fpr64 = DUPv2i32lane killed %7, 0
%0:fpr64 = COPY %11
bb.1:
%9:fpr64 = FMULv2f32 %5, %0, implicit $fpcr
%10:fpr64 = FADDv2f32 killed %9, %6, implicit $fpcr
STRDui killed %10, %4, 0 :: (store 8, align 16)
B %bb.1
...
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