llvm/llvm/test/CodeGen/AArch64/sve-pr92779.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64 -mattr=+sve2 < %s | FileCheck %s

define void @main(ptr %0) {
; CHECK-LABEL: main:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    mov z0.d, #0 // =0x0
; CHECK-NEXT:    ptrue p0.d, vl1
; CHECK-NEXT:    mov z1.d, z0.d
; CHECK-NEXT:    ext z1.b, z1.b, z0.b, #8
; CHECK-NEXT:    uzp1 v1.2s, v0.2s, v1.2s
; CHECK-NEXT:    neg v1.2s, v1.2s
; CHECK-NEXT:    smov x8, v1.s[0]
; CHECK-NEXT:    smov x9, v1.s[1]
; CHECK-NEXT:    mov z0.d, p0/m, x8
; CHECK-NEXT:    mov z0.d, p0/m, x9
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    st1d { z0.d }, p0, [x0]
; CHECK-NEXT:    ret
"entry":
  %1 = bitcast <vscale x 2 x i64> zeroinitializer to <vscale x 4 x i32>
  %a = extractelement <vscale x 4 x i32> %1, i64 0
  %b = insertelement <2 x i32> zeroinitializer, i32 %a, i64 0
  %2 = bitcast <vscale x 2 x i64> zeroinitializer to <vscale x 4 x i32>
  %c = extractelement <vscale x 4 x i32> %2, i64 2
  %d = insertelement <2 x i32> %b, i32 %c, i64 1
  %e = sub <2 x i32> zeroinitializer, %d
  %f = extractelement <2 x i32> %e, i64 0
  %g = sext i32 %f to i64
  %h = insertelement <vscale x 2 x i64> zeroinitializer, i64 %g, i64 0
  %i = extractelement <2 x i32> %e, i64 1
  %j = sext i32 %i to i64
  %k = insertelement <vscale x 2 x i64> %h, i64 %j, i64 0
  store <vscale x 2 x i64> %k, ptr %0, align 16
  ret void
}