llvm/llvm/test/CodeGen/AArch64/peephole-orr.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux -verify-machineinstrs %s | FileCheck %s

---
name: copy_multiple_uses
tracksRegLiveness: true
body: |
  ; CHECK-LABEL: name: copy_multiple_uses
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $w0, $q0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:fpr128 = COPY $q0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32sp = COPY $w0
  ; CHECK-NEXT:   B %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY2]], 1, 0, implicit-def $nzcv
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
  ; CHECK-NEXT:   [[FMOVSWr:%[0-9]+]]:gpr32 = FMOVSWr [[COPY3]]
  ; CHECK-NEXT:   [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[FMOVSWr]], [[SUBSWri]]
  ; CHECK-NEXT:   Bcc 2, %bb.1, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   $w0 = COPY [[ADDWrr]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0.entry:
    liveins: $w0, $q0
    %0:fpr128 = COPY $q0
    %1:gpr32 = COPY $w0
    %6:gpr32sp = COPY $w0
    B %bb.1

  bb.1:
    %7:gpr32 = SUBSWri %6, 1, 0, implicit-def $nzcv
    %2:gpr32 = COPY %0.ssub:fpr128
    %3:gpr32 = ORRWrs $wzr, %2:gpr32, 0
    %5:gpr32 = ADDWrr %2:gpr32, %7:gpr32
    Bcc 2, %bb.1, implicit $nzcv
    B %bb.2

  bb.2:
    $w0 = COPY %5
    RET_ReallyLR implicit $w0