llvm/llvm/test/CodeGen/AArch64/fix-shuffle-vector-be-rev.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefix=CHECKLE
; RUN: llc < %s -mtriple=aarch64_be | FileCheck %s --check-prefix=CHECKBE

define <4 x i16> @test_reconstructshuffle(<16 x i8> %a, <16 x i8> %b) nounwind {
; CHECKLE-LABEL: test_reconstructshuffle:
; CHECKLE:       // %bb.0:
; CHECKLE-NEXT:    umov w8, v0.b[3]
; CHECKLE-NEXT:    umov w9, v0.b[2]
; CHECKLE-NEXT:    fmov s2, w8
; CHECKLE-NEXT:    umov w8, v0.b[1]
; CHECKLE-NEXT:    mov v2.h[1], w9
; CHECKLE-NEXT:    mov v2.h[2], w8
; CHECKLE-NEXT:    umov w8, v0.b[0]
; CHECKLE-NEXT:    ext v0.16b, v1.16b, v1.16b, #8
; CHECKLE-NEXT:    mov v2.h[3], w8
; CHECKLE-NEXT:    zip2 v0.8b, v0.8b, v0.8b
; CHECKLE-NEXT:    add v0.4h, v2.4h, v0.4h
; CHECKLE-NEXT:    bic v0.4h, #255, lsl #8
; CHECKLE-NEXT:    ret
;
; CHECKBE-LABEL: test_reconstructshuffle:
; CHECKBE:       // %bb.0:
; CHECKBE-NEXT:    rev64 v0.16b, v0.16b
; CHECKBE-NEXT:    rev64 v1.16b, v1.16b
; CHECKBE-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
; CHECKBE-NEXT:    ext v1.16b, v1.16b, v1.16b, #8
; CHECKBE-NEXT:    umov w8, v0.b[3]
; CHECKBE-NEXT:    umov w9, v0.b[2]
; CHECKBE-NEXT:    fmov s2, w8
; CHECKBE-NEXT:    umov w8, v0.b[1]
; CHECKBE-NEXT:    mov v2.h[1], w9
; CHECKBE-NEXT:    mov v2.h[2], w8
; CHECKBE-NEXT:    umov w8, v0.b[0]
; CHECKBE-NEXT:    ext v0.16b, v1.16b, v1.16b, #8
; CHECKBE-NEXT:    mov v2.h[3], w8
; CHECKBE-NEXT:    zip2 v0.8b, v0.8b, v0.8b
; CHECKBE-NEXT:    add v0.4h, v2.4h, v0.4h
; CHECKBE-NEXT:    bic v0.4h, #255, lsl #8
; CHECKBE-NEXT:    rev64 v0.4h, v0.4h
; CHECKBE-NEXT:    ret
  %tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
  %tmp2 = shufflevector <16 x i8> %b, <16 x i8> undef, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
  %tmp3 = add <4 x i8> %tmp1, %tmp2
  %tmp4 = zext <4 x i8> %tmp3 to <4 x i16>
  ret <4 x i16> %tmp4
}