llvm/llvm/test/CodeGen/AArch64/extractvector-oob-load.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=aarch64-linux-gnu -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s

---
name:            f
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
liveins:
  - { reg: '$x0' }
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: f
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
    ; CHECK-NEXT: $x0 = COPY [[DEF]](s64)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %0:_(p0) = COPY $x0
    %3:_(s64) = G_CONSTANT i64 224567957
    %1:_(<3 x s64>) = G_LOAD %0(p0) :: (load (<3 x s64>), align 32)
    %2:_(s64) = G_EXTRACT_VECTOR_ELT %1(<3 x s64>), %3(s64)
    $x0 = COPY %2(s64)
    RET_ReallyLR implicit $x0

...