llvm/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fneg.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s

define void @fneg_v8f32(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: fneg_v8f32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvld $xr0, $a1, 0
; CHECK-NEXT:    xvbitrevi.w $xr0, $xr0, 31
; CHECK-NEXT:    xvst $xr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %v0 = load <8 x float>, ptr %a0
  %v1 = fneg <8 x float> %v0
  store <8 x float> %v1, ptr %res
  ret void
}
define void @fneg_v4f64(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: fneg_v4f64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvld $xr0, $a1, 0
; CHECK-NEXT:    xvbitrevi.d $xr0, $xr0, 63
; CHECK-NEXT:    xvst $xr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %v0 = load <4 x double>, ptr %a0
  %v1 = fneg <4 x double> %v0
  store <4 x double> %v1, ptr %res
  ret void
}