llvm/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptosi.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s

define void @fptosi_v8f32_v8i32(ptr %res, ptr %in){
; CHECK-LABEL: fptosi_v8f32_v8i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvld $xr0, $a1, 0
; CHECK-NEXT:    xvftintrz.w.s $xr0, $xr0
; CHECK-NEXT:    xvst $xr0, $a0, 0
; CHECK-NEXT:    ret
  %v0 = load <8 x float>, ptr %in
  %v1 = fptosi <8 x float> %v0 to <8 x i32>
  store <8 x i32> %v1, ptr %res
  ret void
}

define void @fptosi_v4f64_v4i64(ptr %res, ptr %in){
; CHECK-LABEL: fptosi_v4f64_v4i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvld $xr0, $a1, 0
; CHECK-NEXT:    xvftintrz.l.d $xr0, $xr0
; CHECK-NEXT:    xvst $xr0, $a0, 0
; CHECK-NEXT:    ret
  %v0 = load <4 x double>, ptr %in
  %v1 = fptosi <4 x double> %v0 to <4 x i64>
  store <4 x i64> %v1, ptr %res
  ret void
}

define void @fptosi_v4f64_v4i32(ptr %res, ptr %in){
; CHECK-LABEL: fptosi_v4f64_v4i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvld $xr0, $a1, 0
; CHECK-NEXT:    xvpermi.d $xr1, $xr0, 238
; CHECK-NEXT:    xvfcvt.s.d $xr0, $xr1, $xr0
; CHECK-NEXT:    xvftintrz.w.s $xr0, $xr0
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
  %v0 = load <4 x double>, ptr %in
  %v1 = fptosi <4 x double> %v0 to <4 x i32>
  store <4 x i32> %v1, ptr %res
  ret void
}

define void @fptosi_v4f32_v4i64(ptr %res, ptr %in){
; CHECK-LABEL: fptosi_v4f32_v4i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vftintrz.w.s $vr0, $vr0
; CHECK-NEXT:    vext2xv.d.w $xr0, $xr0
; CHECK-NEXT:    xvst $xr0, $a0, 0
; CHECK-NEXT:    ret
  %v0 = load <4 x float>, ptr %in
  %v1 = fptosi <4 x float> %v0 to <4 x i64>
  store <4 x i64> %v1, ptr %res
  ret void
}