; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+f,+d < %s | FileCheck %s --check-prefix=LA64
; Check the GHC call convention works (la64)
@base = external dso_local global i64 ; assigned to register: s0
@sp = external dso_local global i64 ; assigned to register: s1
@hp = external dso_local global i64 ; assigned to register: s2
@r1 = external dso_local global i64 ; assigned to register: s3
@r2 = external dso_local global i64 ; assigned to register: s4
@r3 = external dso_local global i64 ; assigned to register: s5
@r4 = external dso_local global i64 ; assigned to register: s6
@r5 = external dso_local global i64 ; assigned to register: s7
@splim = external dso_local global i64 ; assigned to register: s8
@f1 = external dso_local global float ; assigned to register: fs0
@f2 = external dso_local global float ; assigned to register: fs1
@f3 = external dso_local global float ; assigned to register: fs2
@f4 = external dso_local global float ; assigned to register: fs3
@d1 = external dso_local global double ; assigned to register: fs4
@d2 = external dso_local global double ; assigned to register: fs5
@d3 = external dso_local global double ; assigned to register: fs6
@d4 = external dso_local global double ; assigned to register: fs7
define ghccc void @foo() nounwind {
; LA64-LABEL: foo:
; LA64: # %bb.0: # %entry
; LA64-NEXT: pcalau12i $a0, %pc_hi20(d4)
; LA64-NEXT: fld.d $fs7, $a0, %pc_lo12(d4)
; LA64-NEXT: pcalau12i $a0, %pc_hi20(d3)
; LA64-NEXT: fld.d $fs6, $a0, %pc_lo12(d3)
; LA64-NEXT: pcalau12i $a0, %pc_hi20(d2)
; LA64-NEXT: fld.d $fs5, $a0, %pc_lo12(d2)
; LA64-NEXT: pcalau12i $a0, %pc_hi20(d1)
; LA64-NEXT: fld.d $fs4, $a0, %pc_lo12(d1)
; LA64-NEXT: pcalau12i $a0, %pc_hi20(f4)
; LA64-NEXT: fld.s $fs3, $a0, %pc_lo12(f4)
; LA64-NEXT: pcalau12i $a0, %pc_hi20(f3)
; LA64-NEXT: fld.s $fs2, $a0, %pc_lo12(f3)
; LA64-NEXT: pcalau12i $a0, %pc_hi20(f2)
; LA64-NEXT: fld.s $fs1, $a0, %pc_lo12(f2)
; LA64-NEXT: pcalau12i $a0, %pc_hi20(f1)
; LA64-NEXT: fld.s $fs0, $a0, %pc_lo12(f1)
; LA64-NEXT: pcalau12i $a0, %pc_hi20(splim)
; LA64-NEXT: ld.d $s8, $a0, %pc_lo12(splim)
; LA64-NEXT: pcalau12i $a0, %pc_hi20(r5)
; LA64-NEXT: ld.d $s7, $a0, %pc_lo12(r5)
; LA64-NEXT: pcalau12i $a0, %pc_hi20(r4)
; LA64-NEXT: ld.d $s6, $a0, %pc_lo12(r4)
; LA64-NEXT: pcalau12i $a0, %pc_hi20(r3)
; LA64-NEXT: ld.d $s5, $a0, %pc_lo12(r3)
; LA64-NEXT: pcalau12i $a0, %pc_hi20(r2)
; LA64-NEXT: ld.d $s4, $a0, %pc_lo12(r2)
; LA64-NEXT: pcalau12i $a0, %pc_hi20(r1)
; LA64-NEXT: ld.d $s3, $a0, %pc_lo12(r1)
; LA64-NEXT: pcalau12i $a0, %pc_hi20(hp)
; LA64-NEXT: ld.d $s2, $a0, %pc_lo12(hp)
; LA64-NEXT: pcalau12i $a0, %pc_hi20(sp)
; LA64-NEXT: ld.d $s1, $a0, %pc_lo12(sp)
; LA64-NEXT: pcalau12i $a0, %pc_hi20(base)
; LA64-NEXT: ld.d $s0, $a0, %pc_lo12(base)
; LA64-NEXT: b %plt(bar)
entry:
%0 = load double, ptr @d4
%1 = load double, ptr @d3
%2 = load double, ptr @d2
%3 = load double, ptr @d1
%4 = load float, ptr @f4
%5 = load float, ptr @f3
%6 = load float, ptr @f2
%7 = load float, ptr @f1
%8 = load i64, ptr @splim
%9 = load i64, ptr @r5
%10 = load i64, ptr @r4
%11 = load i64, ptr @r3
%12 = load i64, ptr @r2
%13 = load i64, ptr @r1
%14 = load i64, ptr @hp
%15 = load i64, ptr @sp
%16 = load i64, ptr @base
tail call ghccc void @bar(i64 %16, i64 %15, i64 %14, i64 %13, i64 %12,
i64 %11, i64 %10, i64 %9, i64 %8, float %7, float %6,
float %5, float %4, double %3, double %2, double %1, double %0) nounwind
ret void
}
declare ghccc void @bar(i64, i64, i64, i64, i64, i64, i64, i64, i64,
float, float, float, float,
double, double, double, double)
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