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llvm/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ftint.ll 

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s

declare <4 x i32> @llvm.loongarch.lsx.vftintrne.w.s(<4 x float>)

define <4 x i32> @lsx_vftintrne_w_s(<4 x float> %va) nounwind {
; CHECK-LABEL: lsx_vftintrne_w_s:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrne.w.s $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vftintrne.w.s(<4 x float> %va)
  ret <4 x i32> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vftintrne.l.d(<2 x double>)

define <2 x i64> @lsx_vftintrne_l_d(<2 x double> %va) nounwind {
; CHECK-LABEL: lsx_vftintrne_l_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrne.l.d $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vftintrne.l.d(<2 x double> %va)
  ret <2 x i64> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vftintrz.w.s(<4 x float>)

define <4 x i32> @lsx_vftintrz_w_s(<4 x float> %va) nounwind {
; CHECK-LABEL: lsx_vftintrz_w_s:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrz.w.s $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vftintrz.w.s(<4 x float> %va)
  ret <4 x i32> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vftintrz.l.d(<2 x double>)

define <2 x i64> @lsx_vftintrz_l_d(<2 x double> %va) nounwind {
; CHECK-LABEL: lsx_vftintrz_l_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrz.l.d $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vftintrz.l.d(<2 x double> %va)
  ret <2 x i64> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vftintrp.w.s(<4 x float>)

define <4 x i32> @lsx_vftintrp_w_s(<4 x float> %va) nounwind {
; CHECK-LABEL: lsx_vftintrp_w_s:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrp.w.s $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vftintrp.w.s(<4 x float> %va)
  ret <4 x i32> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vftintrp.l.d(<2 x double>)

define <2 x i64> @lsx_vftintrp_l_d(<2 x double> %va) nounwind {
; CHECK-LABEL: lsx_vftintrp_l_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrp.l.d $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vftintrp.l.d(<2 x double> %va)
  ret <2 x i64> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vftintrm.w.s(<4 x float>)

define <4 x i32> @lsx_vftintrm_w_s(<4 x float> %va) nounwind {
; CHECK-LABEL: lsx_vftintrm_w_s:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrm.w.s $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vftintrm.w.s(<4 x float> %va)
  ret <4 x i32> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vftintrm.l.d(<2 x double>)

define <2 x i64> @lsx_vftintrm_l_d(<2 x double> %va) nounwind {
; CHECK-LABEL: lsx_vftintrm_l_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrm.l.d $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vftintrm.l.d(<2 x double> %va)
  ret <2 x i64> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vftint.w.s(<4 x float>)

define <4 x i32> @lsx_vftint_w_s(<4 x float> %va) nounwind {
; CHECK-LABEL: lsx_vftint_w_s:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftint.w.s $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vftint.w.s(<4 x float> %va)
  ret <4 x i32> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vftint.l.d(<2 x double>)

define <2 x i64> @lsx_vftint_l_d(<2 x double> %va) nounwind {
; CHECK-LABEL: lsx_vftint_l_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftint.l.d $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vftint.l.d(<2 x double> %va)
  ret <2 x i64> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vftintrz.wu.s(<4 x float>)

define <4 x i32> @lsx_vftintrz_wu_s(<4 x float> %va) nounwind {
; CHECK-LABEL: lsx_vftintrz_wu_s:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrz.wu.s $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vftintrz.wu.s(<4 x float> %va)
  ret <4 x i32> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vftintrz.lu.d(<2 x double>)

define <2 x i64> @lsx_vftintrz_lu_d(<2 x double> %va) nounwind {
; CHECK-LABEL: lsx_vftintrz_lu_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrz.lu.d $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vftintrz.lu.d(<2 x double> %va)
  ret <2 x i64> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vftint.wu.s(<4 x float>)

define <4 x i32> @lsx_vftint_wu_s(<4 x float> %va) nounwind {
; CHECK-LABEL: lsx_vftint_wu_s:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftint.wu.s $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vftint.wu.s(<4 x float> %va)
  ret <4 x i32> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vftint.lu.d(<2 x double>)

define <2 x i64> @lsx_vftint_lu_d(<2 x double> %va) nounwind {
; CHECK-LABEL: lsx_vftint_lu_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftint.lu.d $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vftint.lu.d(<2 x double> %va)
  ret <2 x i64> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vftintrne.w.d(<2 x double>, <2 x double>)

define <4 x i32> @lsx_vftintrne_w_d(<2 x double> %va, <2 x double> %vb) nounwind {
; CHECK-LABEL: lsx_vftintrne_w_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrne.w.d $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vftintrne.w.d(<2 x double> %va, <2 x double> %vb)
  ret <4 x i32> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vftintrz.w.d(<2 x double>, <2 x double>)

define <4 x i32> @lsx_vftintrz_w_d(<2 x double> %va, <2 x double> %vb) nounwind {
; CHECK-LABEL: lsx_vftintrz_w_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrz.w.d $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vftintrz.w.d(<2 x double> %va, <2 x double> %vb)
  ret <4 x i32> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vftintrp.w.d(<2 x double>, <2 x double>)

define <4 x i32> @lsx_vftintrp_w_d(<2 x double> %va, <2 x double> %vb) nounwind {
; CHECK-LABEL: lsx_vftintrp_w_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrp.w.d $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vftintrp.w.d(<2 x double> %va, <2 x double> %vb)
  ret <4 x i32> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vftintrm.w.d(<2 x double>, <2 x double>)

define <4 x i32> @lsx_vftintrm_w_d(<2 x double> %va, <2 x double> %vb) nounwind {
; CHECK-LABEL: lsx_vftintrm_w_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrm.w.d $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vftintrm.w.d(<2 x double> %va, <2 x double> %vb)
  ret <4 x i32> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vftint.w.d(<2 x double>, <2 x double>)

define <4 x i32> @lsx_vftint_w_d(<2 x double> %va, <2 x double> %vb) nounwind {
; CHECK-LABEL: lsx_vftint_w_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftint.w.d $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vftint.w.d(<2 x double> %va, <2 x double> %vb)
  ret <4 x i32> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vftintrnel.l.s(<4 x float>)

define <2 x i64> @lsx_vftintrnel_l_s(<4 x float> %va) nounwind {
; CHECK-LABEL: lsx_vftintrnel_l_s:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrnel.l.s $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vftintrnel.l.s(<4 x float> %va)
  ret <2 x i64> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vftintrneh.l.s(<4 x float>)

define <2 x i64> @lsx_vftintrneh_l_s(<4 x float> %va) nounwind {
; CHECK-LABEL: lsx_vftintrneh_l_s:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrneh.l.s $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vftintrneh.l.s(<4 x float> %va)
  ret <2 x i64> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vftintrzl.l.s(<4 x float>)

define <2 x i64> @lsx_vftintrzl_l_s(<4 x float> %va) nounwind {
; CHECK-LABEL: lsx_vftintrzl_l_s:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrzl.l.s $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vftintrzl.l.s(<4 x float> %va)
  ret <2 x i64> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vftintrzh.l.s(<4 x float>)

define <2 x i64> @lsx_vftintrzh_l_s(<4 x float> %va) nounwind {
; CHECK-LABEL: lsx_vftintrzh_l_s:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrzh.l.s $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vftintrzh.l.s(<4 x float> %va)
  ret <2 x i64> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vftintrpl.l.s(<4 x float>)

define <2 x i64> @lsx_vftintrpl_l_s(<4 x float> %va) nounwind {
; CHECK-LABEL: lsx_vftintrpl_l_s:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrpl.l.s $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vftintrpl.l.s(<4 x float> %va)
  ret <2 x i64> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vftintrph.l.s(<4 x float>)

define <2 x i64> @lsx_vftintrph_l_s(<4 x float> %va) nounwind {
; CHECK-LABEL: lsx_vftintrph_l_s:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrph.l.s $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vftintrph.l.s(<4 x float> %va)
  ret <2 x i64> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vftintrml.l.s(<4 x float>)

define <2 x i64> @lsx_vftintrml_l_s(<4 x float> %va) nounwind {
; CHECK-LABEL: lsx_vftintrml_l_s:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrml.l.s $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vftintrml.l.s(<4 x float> %va)
  ret <2 x i64> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vftintrmh.l.s(<4 x float>)

define <2 x i64> @lsx_vftintrmh_l_s(<4 x float> %va) nounwind {
; CHECK-LABEL: lsx_vftintrmh_l_s:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintrmh.l.s $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vftintrmh.l.s(<4 x float> %va)
  ret <2 x i64> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vftintl.l.s(<4 x float>)

define <2 x i64> @lsx_vftintl_l_s(<4 x float> %va) nounwind {
; CHECK-LABEL: lsx_vftintl_l_s:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftintl.l.s $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vftintl.l.s(<4 x float> %va)
  ret <2 x i64> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vftinth.l.s(<4 x float>)

define <2 x i64> @lsx_vftinth_l_s(<4 x float> %va) nounwind {
; CHECK-LABEL: lsx_vftinth_l_s:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vftinth.l.s $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vftinth.l.s(<4 x float> %va)
  ret <2 x i64> %res
}