; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare i32 @llvm.loongarch.lsx.bz.b(<16 x i8>)
define i32 @lsx_bz_b(<16 x i8> %va) nounwind {
; CHECK-LABEL: lsx_bz_b:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetanyeqz.b $fcc0, $vr0
; CHECK-NEXT: bcnez $fcc0, .LBB0_2
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: addi.w $a0, $zero, 0
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2: # %entry
; CHECK-NEXT: addi.w $a0, $zero, 1
; CHECK-NEXT: ret
entry:
%res = call i32 @llvm.loongarch.lsx.bz.b(<16 x i8> %va)
ret i32 %res
}
declare i32 @llvm.loongarch.lsx.bz.h(<8 x i16>)
define i32 @lsx_bz_h(<8 x i16> %va) nounwind {
; CHECK-LABEL: lsx_bz_h:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetanyeqz.h $fcc0, $vr0
; CHECK-NEXT: bcnez $fcc0, .LBB1_2
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: addi.w $a0, $zero, 0
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2: # %entry
; CHECK-NEXT: addi.w $a0, $zero, 1
; CHECK-NEXT: ret
entry:
%res = call i32 @llvm.loongarch.lsx.bz.h(<8 x i16> %va)
ret i32 %res
}
declare i32 @llvm.loongarch.lsx.bz.w(<4 x i32>)
define i32 @lsx_bz_w(<4 x i32> %va) nounwind {
; CHECK-LABEL: lsx_bz_w:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetanyeqz.w $fcc0, $vr0
; CHECK-NEXT: bcnez $fcc0, .LBB2_2
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: addi.w $a0, $zero, 0
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB2_2: # %entry
; CHECK-NEXT: addi.w $a0, $zero, 1
; CHECK-NEXT: ret
entry:
%res = call i32 @llvm.loongarch.lsx.bz.w(<4 x i32> %va)
ret i32 %res
}
declare i32 @llvm.loongarch.lsx.bz.d(<2 x i64>)
define i32 @lsx_bz_d(<2 x i64> %va) nounwind {
; CHECK-LABEL: lsx_bz_d:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetanyeqz.d $fcc0, $vr0
; CHECK-NEXT: bcnez $fcc0, .LBB3_2
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: addi.w $a0, $zero, 0
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB3_2: # %entry
; CHECK-NEXT: addi.w $a0, $zero, 1
; CHECK-NEXT: ret
entry:
%res = call i32 @llvm.loongarch.lsx.bz.d(<2 x i64> %va)
ret i32 %res
}