llvm/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s

declare <16 x i8> @llvm.loongarch.lsx.vsrl.b(<16 x i8>, <16 x i8>)

define <16 x i8> @lsx_vsrl_b(<16 x i8> %va, <16 x i8> %vb) nounwind {
; CHECK-LABEL: lsx_vsrl_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsrl.b $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i8> @llvm.loongarch.lsx.vsrl.b(<16 x i8> %va, <16 x i8> %vb)
  ret <16 x i8> %res
}

declare <8 x i16> @llvm.loongarch.lsx.vsrl.h(<8 x i16>, <8 x i16>)

define <8 x i16> @lsx_vsrl_h(<8 x i16> %va, <8 x i16> %vb) nounwind {
; CHECK-LABEL: lsx_vsrl_h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsrl.h $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i16> @llvm.loongarch.lsx.vsrl.h(<8 x i16> %va, <8 x i16> %vb)
  ret <8 x i16> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vsrl.w(<4 x i32>, <4 x i32>)

define <4 x i32> @lsx_vsrl_w(<4 x i32> %va, <4 x i32> %vb) nounwind {
; CHECK-LABEL: lsx_vsrl_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsrl.w $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vsrl.w(<4 x i32> %va, <4 x i32> %vb)
  ret <4 x i32> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vsrl.d(<2 x i64>, <2 x i64>)

define <2 x i64> @lsx_vsrl_d(<2 x i64> %va, <2 x i64> %vb) nounwind {
; CHECK-LABEL: lsx_vsrl_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsrl.d $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vsrl.d(<2 x i64> %va, <2 x i64> %vb)
  ret <2 x i64> %res
}

declare <16 x i8> @llvm.loongarch.lsx.vsrli.b(<16 x i8>, i32)

define <16 x i8> @lsx_vsrli_b(<16 x i8> %va) nounwind {
; CHECK-LABEL: lsx_vsrli_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsrli.b $vr0, $vr0, 7
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i8> @llvm.loongarch.lsx.vsrli.b(<16 x i8> %va, i32 7)
  ret <16 x i8> %res
}

declare <8 x i16> @llvm.loongarch.lsx.vsrli.h(<8 x i16>, i32)

define <8 x i16> @lsx_vsrli_h(<8 x i16> %va) nounwind {
; CHECK-LABEL: lsx_vsrli_h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsrli.h $vr0, $vr0, 15
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i16> @llvm.loongarch.lsx.vsrli.h(<8 x i16> %va, i32 15)
  ret <8 x i16> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vsrli.w(<4 x i32>, i32)

define <4 x i32> @lsx_vsrli_w(<4 x i32> %va) nounwind {
; CHECK-LABEL: lsx_vsrli_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsrli.w $vr0, $vr0, 31
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vsrli.w(<4 x i32> %va, i32 31)
  ret <4 x i32> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vsrli.d(<2 x i64>, i32)

define <2 x i64> @lsx_vsrli_d(<2 x i64> %va) nounwind {
; CHECK-LABEL: lsx_vsrli_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsrli.d $vr0, $vr0, 63
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vsrli.d(<2 x i64> %va, i32 63)
  ret <2 x i64> %res
}