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llvm/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll 

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v \
; RUN:     -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
; RUN:     --check-prefixes=CHECK,ZVFH
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v \
; RUN:     -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
; RUN:     --check-prefixes=CHECK,ZVFH
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v \
; RUN:     -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
; RUN:     --check-prefixes=CHECK,ZVFHMIN
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v \
; RUN:     -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
; RUN:     --check-prefixes=CHECK,ZVFHMIN

define <vscale x 1 x bfloat> @nxv1bf16(<vscale x 1 x bfloat> %v) {
; CHECK-LABEL: nxv1bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lui a0, 8
; CHECK-NEXT:    addi a0, a0, -1
; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT:    vand.vx v8, v8, a0
; CHECK-NEXT:    ret
  %r = call <vscale x 1 x bfloat> @llvm.fabs.nxv1bf16(<vscale x 1 x bfloat> %v)
  ret <vscale x 1 x bfloat> %r
}

define <vscale x 2 x bfloat> @nxv2bf16(<vscale x 2 x bfloat> %v) {
; CHECK-LABEL: nxv2bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lui a0, 8
; CHECK-NEXT:    addi a0, a0, -1
; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; CHECK-NEXT:    vand.vx v8, v8, a0
; CHECK-NEXT:    ret
  %r = call <vscale x 2 x bfloat> @llvm.fabs.nxv2bf16(<vscale x 2 x bfloat> %v)
  ret <vscale x 2 x bfloat> %r
}

define <vscale x 4 x bfloat> @nxv4bf16(<vscale x 4 x bfloat> %v) {
; CHECK-LABEL: nxv4bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lui a0, 8
; CHECK-NEXT:    addi a0, a0, -1
; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT:    vand.vx v8, v8, a0
; CHECK-NEXT:    ret
  %r = call <vscale x 4 x bfloat> @llvm.fabs.nxv4bf16(<vscale x 4 x bfloat> %v)
  ret <vscale x 4 x bfloat> %r
}

define <vscale x 8 x bfloat> @nxv8bf16(<vscale x 8 x bfloat> %v) {
; CHECK-LABEL: nxv8bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lui a0, 8
; CHECK-NEXT:    addi a0, a0, -1
; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT:    vand.vx v8, v8, a0
; CHECK-NEXT:    ret
  %r = call <vscale x 8 x bfloat> @llvm.fabs.nxv8bf16(<vscale x 8 x bfloat> %v)
  ret <vscale x 8 x bfloat> %r
}

define <vscale x 16 x bfloat> @nxv16bf16(<vscale x 16 x bfloat> %v) {
; CHECK-LABEL: nxv16bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lui a0, 8
; CHECK-NEXT:    addi a0, a0, -1
; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
; CHECK-NEXT:    vand.vx v8, v8, a0
; CHECK-NEXT:    ret
  %r = call <vscale x 16 x bfloat> @llvm.fabs.nxv16bf16(<vscale x 16 x bfloat> %v)
  ret <vscale x 16 x bfloat> %r
}

define <vscale x 32 x bfloat> @nxv32bf16(<vscale x 32 x bfloat> %v) {
; CHECK-LABEL: nxv32bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lui a0, 8
; CHECK-NEXT:    addi a0, a0, -1
; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; CHECK-NEXT:    vand.vx v8, v8, a0
; CHECK-NEXT:    ret
  %r = call <vscale x 32 x bfloat> @llvm.fabs.nxv32bf16(<vscale x 32 x bfloat> %v)
  ret <vscale x 32 x bfloat> %r
}

declare <vscale x 1 x half> @llvm.fabs.nxv1f16(<vscale x 1 x half>)

define <vscale x 1 x half> @vfabs_nxv1f16(<vscale x 1 x half> %v) {
; ZVFH-LABEL: vfabs_nxv1f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; ZVFH-NEXT:    vfabs.v v8, v8
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: vfabs_nxv1f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    lui a0, 8
; ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFHMIN-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFHMIN-NEXT:    ret
  %r = call <vscale x 1 x half> @llvm.fabs.nxv1f16(<vscale x 1 x half> %v)
  ret <vscale x 1 x half> %r
}

declare <vscale x 2 x half> @llvm.fabs.nxv2f16(<vscale x 2 x half>)

define <vscale x 2 x half> @vfabs_nxv2f16(<vscale x 2 x half> %v) {
; ZVFH-LABEL: vfabs_nxv2f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
; ZVFH-NEXT:    vfabs.v v8, v8
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: vfabs_nxv2f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    lui a0, 8
; ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFHMIN-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFHMIN-NEXT:    ret
  %r = call <vscale x 2 x half> @llvm.fabs.nxv2f16(<vscale x 2 x half> %v)
  ret <vscale x 2 x half> %r
}

declare <vscale x 4 x half> @llvm.fabs.nxv4f16(<vscale x 4 x half>)

define <vscale x 4 x half> @vfabs_nxv4f16(<vscale x 4 x half> %v) {
; ZVFH-LABEL: vfabs_nxv4f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT:    vfabs.v v8, v8
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: vfabs_nxv4f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    lui a0, 8
; ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFHMIN-NEXT:    ret
  %r = call <vscale x 4 x half> @llvm.fabs.nxv4f16(<vscale x 4 x half> %v)
  ret <vscale x 4 x half> %r
}

declare <vscale x 8 x half> @llvm.fabs.nxv8f16(<vscale x 8 x half>)

define <vscale x 8 x half> @vfabs_nxv8f16(<vscale x 8 x half> %v) {
; ZVFH-LABEL: vfabs_nxv8f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
; ZVFH-NEXT:    vfabs.v v8, v8
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: vfabs_nxv8f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    lui a0, 8
; ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFHMIN-NEXT:    ret
  %r = call <vscale x 8 x half> @llvm.fabs.nxv8f16(<vscale x 8 x half> %v)
  ret <vscale x 8 x half> %r
}

declare <vscale x 16 x half> @llvm.fabs.nxv16f16(<vscale x 16 x half>)

define <vscale x 16 x half> @vfabs_nxv16f16(<vscale x 16 x half> %v) {
; ZVFH-LABEL: vfabs_nxv16f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
; ZVFH-NEXT:    vfabs.v v8, v8
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: vfabs_nxv16f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    lui a0, 8
; ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFHMIN-NEXT:    ret
  %r = call <vscale x 16 x half> @llvm.fabs.nxv16f16(<vscale x 16 x half> %v)
  ret <vscale x 16 x half> %r
}

declare <vscale x 32 x half> @llvm.fabs.nxv32f16(<vscale x 32 x half>)

define <vscale x 32 x half> @vfabs_nxv32f16(<vscale x 32 x half> %v) {
; ZVFH-LABEL: vfabs_nxv32f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
; ZVFH-NEXT:    vfabs.v v8, v8
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: vfabs_nxv32f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    lui a0, 8
; ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFHMIN-NEXT:    ret
  %r = call <vscale x 32 x half> @llvm.fabs.nxv32f16(<vscale x 32 x half> %v)
  ret <vscale x 32 x half> %r
}

declare <vscale x 1 x float> @llvm.fabs.nxv1f32(<vscale x 1 x float>)

define <vscale x 1 x float> @vfabs_nxv1f32(<vscale x 1 x float> %v) {
; CHECK-LABEL: vfabs_nxv1f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %r = call <vscale x 1 x float> @llvm.fabs.nxv1f32(<vscale x 1 x float> %v)
  ret <vscale x 1 x float> %r
}

declare <vscale x 2 x float> @llvm.fabs.nxv2f32(<vscale x 2 x float>)

define <vscale x 2 x float> @vfabs_nxv2f32(<vscale x 2 x float> %v) {
; CHECK-LABEL: vfabs_nxv2f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %r = call <vscale x 2 x float> @llvm.fabs.nxv2f32(<vscale x 2 x float> %v)
  ret <vscale x 2 x float> %r
}

declare <vscale x 4 x float> @llvm.fabs.nxv4f32(<vscale x 4 x float>)

define <vscale x 4 x float> @vfabs_nxv4f32(<vscale x 4 x float> %v) {
; CHECK-LABEL: vfabs_nxv4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %r = call <vscale x 4 x float> @llvm.fabs.nxv4f32(<vscale x 4 x float> %v)
  ret <vscale x 4 x float> %r
}

declare <vscale x 8 x float> @llvm.fabs.nxv8f32(<vscale x 8 x float>)

define <vscale x 8 x float> @vfabs_nxv8f32(<vscale x 8 x float> %v) {
; CHECK-LABEL: vfabs_nxv8f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %r = call <vscale x 8 x float> @llvm.fabs.nxv8f32(<vscale x 8 x float> %v)
  ret <vscale x 8 x float> %r
}

declare <vscale x 16 x float> @llvm.fabs.nxv16f32(<vscale x 16 x float>)

define <vscale x 16 x float> @vfabs_nxv16f32(<vscale x 16 x float> %v) {
; CHECK-LABEL: vfabs_nxv16f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %r = call <vscale x 16 x float> @llvm.fabs.nxv16f32(<vscale x 16 x float> %v)
  ret <vscale x 16 x float> %r
}

declare <vscale x 1 x double> @llvm.fabs.nxv1f64(<vscale x 1 x double>)

define <vscale x 1 x double> @vfabs_nxv1f64(<vscale x 1 x double> %v) {
; CHECK-LABEL: vfabs_nxv1f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %r = call <vscale x 1 x double> @llvm.fabs.nxv1f64(<vscale x 1 x double> %v)
  ret <vscale x 1 x double> %r
}

declare <vscale x 2 x double> @llvm.fabs.nxv2f64(<vscale x 2 x double>)

define <vscale x 2 x double> @vfabs_nxv2f64(<vscale x 2 x double> %v) {
; CHECK-LABEL: vfabs_nxv2f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %r = call <vscale x 2 x double> @llvm.fabs.nxv2f64(<vscale x 2 x double> %v)
  ret <vscale x 2 x double> %r
}

declare <vscale x 4 x double> @llvm.fabs.nxv4f64(<vscale x 4 x double>)

define <vscale x 4 x double> @vfabs_nxv4f64(<vscale x 4 x double> %v) {
; CHECK-LABEL: vfabs_nxv4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %r = call <vscale x 4 x double> @llvm.fabs.nxv4f64(<vscale x 4 x double> %v)
  ret <vscale x 4 x double> %r
}

declare <vscale x 8 x double> @llvm.fabs.nxv8f64(<vscale x 8 x double>)

define <vscale x 8 x double> @vfabs_nxv8f64(<vscale x 8 x double> %v) {
; CHECK-LABEL: vfabs_nxv8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %r = call <vscale x 8 x double> @llvm.fabs.nxv8f64(<vscale x 8 x double> %v)
  ret <vscale x 8 x double> %r
}