llvm/llvm/test/CodeGen/RISCV/rv32zksh-intrinsic.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zksh -verify-machineinstrs < %s \
; RUN:   | FileCheck %s -check-prefix=RV32ZKSH

declare i32 @llvm.riscv.sm3p0(i32);

define i32 @sm3p0_i32(i32 %a) nounwind {
; RV32ZKSH-LABEL: sm3p0_i32:
; RV32ZKSH:       # %bb.0:
; RV32ZKSH-NEXT:    sm3p0 a0, a0
; RV32ZKSH-NEXT:    ret
  %val = call i32 @llvm.riscv.sm3p0(i32 %a)
  ret i32 %val
}

declare i32 @llvm.riscv.sm3p1(i32);

define i32 @sm3p1_i32(i32 %a) nounwind {
; RV32ZKSH-LABEL: sm3p1_i32:
; RV32ZKSH:       # %bb.0:
; RV32ZKSH-NEXT:    sm3p1 a0, a0
; RV32ZKSH-NEXT:    ret
  %val = call i32 @llvm.riscv.sm3p1(i32 %a)
  ret i32 %val
}