llvm/llvm/test/CodeGen/RISCV/pr90652.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc < %s -mtriple=riscv64 | FileCheck %s

define i1 @test(i64 %x, i1 %cond1, i1 %cond2) {
; CHECK-LABEL: test:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    addi a3, a0, 1
; CHECK-NEXT:    slt a0, a3, a0
; CHECK-NEXT:    not a1, a1
; CHECK-NEXT:    and a0, a1, a0
; CHECK-NEXT:    or a0, a2, a0
; CHECK-NEXT:    ret
entry:
  %sadd = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %x, i64 1)
  %ov = extractvalue { i64, i1 } %sadd, 1
  %or = or i1 %cond2, %ov
  %sel = select i1 %cond1, i1 %cond2, i1 %or
  ret i1 %sel
}