# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
---
name: test_1
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
; CHECK-LABEL: name: test_1
; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
; CHECK-NEXT: $x10 = COPY [[SRLI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = G_READ_VLENB
%1:gprb(s64) = G_CONSTANT i64 3
%2:gprb(s64) = G_LSHR %0, %1(s64)
$x10 = COPY %2(s64)
PseudoRET implicit $x10
...
---
name: test_2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
; CHECK-LABEL: name: test_2
; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 2
; CHECK-NEXT: $x10 = COPY [[SRLI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = G_READ_VLENB
%1:gprb(s64) = G_CONSTANT i64 2
%2:gprb(s64) = G_LSHR %0, %1(s64)
$x10 = COPY %2(s64)
PseudoRET implicit $x10
...
---
name: test_3
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
; CHECK-LABEL: name: test_3
; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 3
; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]
; CHECK-NEXT: $x10 = COPY [[MUL]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = G_READ_VLENB
%1:gprb(s64) = G_CONSTANT i64 3
%2:gprb(s64) = G_LSHR %0, %1(s64)
%3:gprb(s64) = G_CONSTANT i64 3
%4:gprb(s64) = G_MUL %2, %3
$x10 = COPY %4(s64)
PseudoRET implicit $x10
...
---
name: test_4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
; CHECK-LABEL: name: test_4
; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 1
; CHECK-NEXT: $x10 = COPY [[SRLI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = G_READ_VLENB
%1:gprb(s64) = G_CONSTANT i64 1
%2:gprb(s64) = G_LSHR %0, %1(s64)
$x10 = COPY %2(s64)
PseudoRET implicit $x10
...
---
name: test_8
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
; CHECK-LABEL: name: test_8
; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = G_READ_VLENB
$x10 = COPY %0(s64)
PseudoRET implicit $x10
...
---
name: test_16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
; CHECK-LABEL: name: test_16
; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[PseudoReadVLENB]], 1
; CHECK-NEXT: $x10 = COPY [[SLLI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = G_READ_VLENB
%1:gprb(s64) = G_CONSTANT i64 1
%2:gprb(s64) = G_SHL %0, %1(s64)
$x10 = COPY %2(s64)
PseudoRET implicit $x10
...
---
name: test_40
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
; CHECK-LABEL: name: test_40
; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5
; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PseudoReadVLENB]], [[ADDI]]
; CHECK-NEXT: $x10 = COPY [[MUL]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = G_READ_VLENB
%1:gprb(s64) = G_CONSTANT i64 5
%2:gprb(s64) = G_MUL %0, %1
$x10 = COPY %2(s64)
PseudoRET implicit $x10
...
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