vscale32.mir | Explore in Territory

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck  %s

---
name:            test_1_s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_1_s32
    ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
    ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
    ; CHECK-NEXT: $x10 = COPY [[SRLI]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %1:gprb(s32) = G_READ_VLENB
    %2:gprb(s32) = G_CONSTANT i32 3
    %0:gprb(s32) = G_LSHR %1, %2(s32)
    $x10 = COPY %0(s32)
    PseudoRET implicit $x10

...
---
name:            test_2_s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_2_s32
    ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
    ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 2
    ; CHECK-NEXT: $x10 = COPY [[SRLI]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %1:gprb(s32) = G_READ_VLENB
    %2:gprb(s32) = G_CONSTANT i32 2
    %0:gprb(s32) = G_LSHR %1, %2(s32)
    $x10 = COPY %0(s32)
    PseudoRET implicit $x10

...
---
name:            test_3_s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_3_s32
    ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
    ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 3
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %1:gprb(s32) = G_READ_VLENB
    %2:gprb(s32) = G_CONSTANT i32 3
    %3:gprb(s32) = G_LSHR %1, %2(s32)
    %4:gprb(s32) = G_CONSTANT i32 3
    %0:gprb(s32) = G_MUL %3, %4
    $x10 = COPY %0(s32)
    PseudoRET implicit $x10

...
---
name:            test_4_s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_4_s32
    ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
    ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 1
    ; CHECK-NEXT: $x10 = COPY [[SRLI]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %1:gprb(s32) = G_READ_VLENB
    %2:gprb(s32) = G_CONSTANT i32 1
    %0:gprb(s32) = G_LSHR %1, %2(s32)
    $x10 = COPY %0(s32)
    PseudoRET implicit $x10

...
---
name:            test_8_s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_8_s32
    ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
    ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = G_READ_VLENB
    $x10 = COPY %0(s32)
    PseudoRET implicit $x10

...
---
name:            test_16_s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_16_s32
    ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
    ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[PseudoReadVLENB]], 1
    ; CHECK-NEXT: $x10 = COPY [[SLLI]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %1:gprb(s32) = G_READ_VLENB
    %2:gprb(s32) = G_CONSTANT i32 1
    %0:gprb(s32) = G_SHL %1, %2(s32)
    $x10 = COPY %0(s32)
    PseudoRET implicit $x10

...
---
name:            test_40_s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_40_s32
    ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PseudoReadVLENB]], [[ADDI]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %1:gprb(s32) = G_READ_VLENB
    %2:gprb(s32) = G_CONSTANT i32 5
    %0:gprb(s32) = G_MUL %1, %2
    $x10 = COPY %0(s32)
    PseudoRET implicit $x10

...
---
name:            test_1_s64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_1_s64
    ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
    ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %17:gprb(s32) = G_READ_VLENB
    %18:gprb(s32) = G_CONSTANT i32 3
    %2:gprb(s32) = G_LSHR %17, %18(s32)
    %15:gprb(s32) = G_CONSTANT i32 1
    %9:gprb(s32) = G_MUL %2, %15
    $x10 = COPY %9(s32)
    PseudoRET implicit $x10

...
---
name:            test_2_s64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_2_s64
    ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
    ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 2
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %17:gprb(s32) = G_READ_VLENB
    %18:gprb(s32) = G_CONSTANT i32 3
    %2:gprb(s32) = G_LSHR %17, %18(s32)
    %15:gprb(s32) = G_CONSTANT i32 2
    %9:gprb(s32) = G_MUL %2, %15
    $x10 = COPY %9(s32)
    PseudoRET implicit $x10

...
---
name:            test_3_s64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_3_s64
    ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
    ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 3
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %17:gprb(s32) = G_READ_VLENB
    %18:gprb(s32) = G_CONSTANT i32 3
    %2:gprb(s32) = G_LSHR %17, %18(s32)
    %15:gprb(s32) = G_CONSTANT i32 3
    %9:gprb(s32) = G_MUL %2, %15
    $x10 = COPY %9(s32)
    PseudoRET implicit $x10

...
---
name:            test_4_s64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_4_s64
    ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
    ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 4
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %17:gprb(s32) = G_READ_VLENB
    %18:gprb(s32) = G_CONSTANT i32 3
    %2:gprb(s32) = G_LSHR %17, %18(s32)
    %15:gprb(s32) = G_CONSTANT i32 4
    %9:gprb(s32) = G_MUL %2, %15
    $x10 = COPY %9(s32)
    PseudoRET implicit $x10

...
---
name:            test_8_s64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_8_s64
    ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
    ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %17:gprb(s32) = G_READ_VLENB
    %18:gprb(s32) = G_CONSTANT i32 3
    %2:gprb(s32) = G_LSHR %17, %18(s32)
    %15:gprb(s32) = G_CONSTANT i32 8
    %9:gprb(s32) = G_MUL %2, %15
    $x10 = COPY %9(s32)
    PseudoRET implicit $x10

...
---
name:            test_16_s64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_16_s64
    ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
    ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 16
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %17:gprb(s32) = G_READ_VLENB
    %18:gprb(s32) = G_CONSTANT i32 3
    %2:gprb(s32) = G_LSHR %17, %18(s32)
    %15:gprb(s32) = G_CONSTANT i32 16
    %9:gprb(s32) = G_MUL %2, %15
    $x10 = COPY %9(s32)
    PseudoRET implicit $x10

...
---
name:            test_40_s64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_40_s64
    ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
    ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 40
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %17:gprb(s32) = G_READ_VLENB
    %18:gprb(s32) = G_CONSTANT i32 3
    %2:gprb(s32) = G_LSHR %17, %18(s32)
    %15:gprb(s32) = G_CONSTANT i32 40
    %9:gprb(s32) = G_MUL %2, %15
    $x10 = COPY %9(s32)
    PseudoRET implicit $x10

...
llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale32.mir
