# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
---
name: fcmp_oeq_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_f, $f11_f
; CHECK-LABEL: name: fcmp_oeq_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[FEQ_S:%[0-9]+]]:gpr = nofpexcept FEQ_S [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[FEQ_S]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s32) = COPY $f10_f
%1:fprb(s32) = COPY $f11_f
%4:gprb(s32) = G_FCMP floatpred(oeq), %0(s32), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_ogt_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_f, $f11_f
; CHECK-LABEL: name: fcmp_ogt_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[FLT_S:%[0-9]+]]:gpr = FLT_S [[COPY1]], [[COPY]]
; CHECK-NEXT: $x10 = COPY [[FLT_S]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s32) = COPY $f10_f
%1:fprb(s32) = COPY $f11_f
%4:gprb(s32) = G_FCMP floatpred(ogt), %0(s32), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_oge_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_f, $f11_f
; CHECK-LABEL: name: fcmp_oge_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[FLE_S:%[0-9]+]]:gpr = FLE_S [[COPY1]], [[COPY]]
; CHECK-NEXT: $x10 = COPY [[FLE_S]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s32) = COPY $f10_f
%1:fprb(s32) = COPY $f11_f
%4:gprb(s32) = G_FCMP floatpred(oge), %0(s32), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_olt_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_f, $f11_f
; CHECK-LABEL: name: fcmp_olt_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[FLT_S:%[0-9]+]]:gpr = nofpexcept FLT_S [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[FLT_S]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s32) = COPY $f10_f
%1:fprb(s32) = COPY $f11_f
%4:gprb(s32) = G_FCMP floatpred(olt), %0(s32), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_ole_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_f, $f11_f
; CHECK-LABEL: name: fcmp_ole_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[FLE_S:%[0-9]+]]:gpr = nofpexcept FLE_S [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[FLE_S]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s32) = COPY $f10_f
%1:fprb(s32) = COPY $f11_f
%4:gprb(s32) = G_FCMP floatpred(ole), %0(s32), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_one_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_f, $f11_f
; CHECK-LABEL: name: fcmp_one_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[FLT_S:%[0-9]+]]:gpr = FLT_S [[COPY]], [[COPY1]]
; CHECK-NEXT: [[FLT_S1:%[0-9]+]]:gpr = FLT_S [[COPY1]], [[COPY]]
; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_S]], [[FLT_S1]]
; CHECK-NEXT: $x10 = COPY [[OR]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s32) = COPY $f10_f
%1:fprb(s32) = COPY $f11_f
%4:gprb(s32) = G_FCMP floatpred(one), %0(s32), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_ord_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_f, $f11_f
; CHECK-LABEL: name: fcmp_ord_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[FEQ_S:%[0-9]+]]:gpr = FEQ_S [[COPY]], [[COPY]]
; CHECK-NEXT: [[FEQ_S1:%[0-9]+]]:gpr = FEQ_S [[COPY1]], [[COPY1]]
; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[FEQ_S]], [[FEQ_S1]]
; CHECK-NEXT: $x10 = COPY [[AND]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s32) = COPY $f10_f
%1:fprb(s32) = COPY $f11_f
%4:gprb(s32) = G_FCMP floatpred(ord), %0(s32), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_ueq_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_f, $f11_f
; CHECK-LABEL: name: fcmp_ueq_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[FLT_S:%[0-9]+]]:gpr = FLT_S [[COPY]], [[COPY1]]
; CHECK-NEXT: [[FLT_S1:%[0-9]+]]:gpr = FLT_S [[COPY1]], [[COPY]]
; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_S]], [[FLT_S1]]
; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[OR]], 1
; CHECK-NEXT: $x10 = COPY [[XORI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s32) = COPY $f10_f
%1:fprb(s32) = COPY $f11_f
%4:gprb(s32) = G_FCMP floatpred(ueq), %0(s32), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_ugt_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_f, $f11_f
; CHECK-LABEL: name: fcmp_ugt_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[FLE_S:%[0-9]+]]:gpr = FLE_S [[COPY]], [[COPY1]]
; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLE_S]], 1
; CHECK-NEXT: $x10 = COPY [[XORI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s32) = COPY $f10_f
%1:fprb(s32) = COPY $f11_f
%4:gprb(s32) = G_FCMP floatpred(ugt), %0(s32), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_uge_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_f, $f11_f
; CHECK-LABEL: name: fcmp_uge_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[FLT_S:%[0-9]+]]:gpr = FLT_S [[COPY]], [[COPY1]]
; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLT_S]], 1
; CHECK-NEXT: $x10 = COPY [[XORI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s32) = COPY $f10_f
%1:fprb(s32) = COPY $f11_f
%4:gprb(s32) = G_FCMP floatpred(uge), %0(s32), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_ult_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_f, $f11_f
; CHECK-LABEL: name: fcmp_ult_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[FLE_S:%[0-9]+]]:gpr = FLE_S [[COPY1]], [[COPY]]
; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLE_S]], 1
; CHECK-NEXT: $x10 = COPY [[XORI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s32) = COPY $f10_f
%1:fprb(s32) = COPY $f11_f
%4:gprb(s32) = G_FCMP floatpred(ult), %0(s32), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_ule_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_f, $f11_f
; CHECK-LABEL: name: fcmp_ule_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[FLT_S:%[0-9]+]]:gpr = FLT_S [[COPY1]], [[COPY]]
; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLT_S]], 1
; CHECK-NEXT: $x10 = COPY [[XORI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s32) = COPY $f10_f
%1:fprb(s32) = COPY $f11_f
%4:gprb(s32) = G_FCMP floatpred(ule), %0(s32), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_une_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_f, $f11_f
; CHECK-LABEL: name: fcmp_une_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[FEQ_S:%[0-9]+]]:gpr = FEQ_S [[COPY]], [[COPY1]]
; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FEQ_S]], 1
; CHECK-NEXT: $x10 = COPY [[XORI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s32) = COPY $f10_f
%1:fprb(s32) = COPY $f11_f
%4:gprb(s32) = G_FCMP floatpred(une), %0(s32), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_uno_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_f, $f11_f
; CHECK-LABEL: name: fcmp_uno_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[FEQ_S:%[0-9]+]]:gpr = FEQ_S [[COPY]], [[COPY]]
; CHECK-NEXT: [[FEQ_S1:%[0-9]+]]:gpr = FEQ_S [[COPY1]], [[COPY1]]
; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[FEQ_S]], [[FEQ_S1]]
; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[AND]], 1
; CHECK-NEXT: $x10 = COPY [[XORI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s32) = COPY $f10_f
%1:fprb(s32) = COPY $f11_f
%4:gprb(s32) = G_FCMP floatpred(uno), %0(s32), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_oeq_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_d, $f11_d
; CHECK-LABEL: name: fcmp_oeq_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[FEQ_D:%[0-9]+]]:gpr = nofpexcept FEQ_D [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[FEQ_D]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s64) = COPY $f10_d
%1:fprb(s64) = COPY $f11_d
%4:gprb(s32) = G_FCMP floatpred(oeq), %0(s64), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_ogt_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_d, $f11_d
; CHECK-LABEL: name: fcmp_ogt_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[FLT_D:%[0-9]+]]:gpr = FLT_D [[COPY1]], [[COPY]]
; CHECK-NEXT: $x10 = COPY [[FLT_D]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s64) = COPY $f10_d
%1:fprb(s64) = COPY $f11_d
%4:gprb(s32) = G_FCMP floatpred(ogt), %0(s64), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_oge_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_d, $f11_d
; CHECK-LABEL: name: fcmp_oge_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[FLE_D:%[0-9]+]]:gpr = FLE_D [[COPY1]], [[COPY]]
; CHECK-NEXT: $x10 = COPY [[FLE_D]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s64) = COPY $f10_d
%1:fprb(s64) = COPY $f11_d
%4:gprb(s32) = G_FCMP floatpred(oge), %0(s64), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_olt_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_d, $f11_d
; CHECK-LABEL: name: fcmp_olt_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[FLT_D:%[0-9]+]]:gpr = nofpexcept FLT_D [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[FLT_D]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s64) = COPY $f10_d
%1:fprb(s64) = COPY $f11_d
%4:gprb(s32) = G_FCMP floatpred(olt), %0(s64), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_ole_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_d, $f11_d
; CHECK-LABEL: name: fcmp_ole_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[FLE_D:%[0-9]+]]:gpr = nofpexcept FLE_D [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[FLE_D]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s64) = COPY $f10_d
%1:fprb(s64) = COPY $f11_d
%4:gprb(s32) = G_FCMP floatpred(ole), %0(s64), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_one_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_d, $f11_d
; CHECK-LABEL: name: fcmp_one_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[FLT_D:%[0-9]+]]:gpr = FLT_D [[COPY]], [[COPY1]]
; CHECK-NEXT: [[FLT_D1:%[0-9]+]]:gpr = FLT_D [[COPY1]], [[COPY]]
; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_D]], [[FLT_D1]]
; CHECK-NEXT: $x10 = COPY [[OR]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s64) = COPY $f10_d
%1:fprb(s64) = COPY $f11_d
%4:gprb(s32) = G_FCMP floatpred(one), %0(s64), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_ord_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_d, $f11_d
; CHECK-LABEL: name: fcmp_ord_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[FEQ_D:%[0-9]+]]:gpr = FEQ_D [[COPY]], [[COPY]]
; CHECK-NEXT: [[FEQ_D1:%[0-9]+]]:gpr = FEQ_D [[COPY1]], [[COPY1]]
; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[FEQ_D]], [[FEQ_D1]]
; CHECK-NEXT: $x10 = COPY [[AND]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s64) = COPY $f10_d
%1:fprb(s64) = COPY $f11_d
%4:gprb(s32) = G_FCMP floatpred(ord), %0(s64), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_ueq_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_d, $f11_d
; CHECK-LABEL: name: fcmp_ueq_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[FLT_D:%[0-9]+]]:gpr = FLT_D [[COPY]], [[COPY1]]
; CHECK-NEXT: [[FLT_D1:%[0-9]+]]:gpr = FLT_D [[COPY1]], [[COPY]]
; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_D]], [[FLT_D1]]
; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[OR]], 1
; CHECK-NEXT: $x10 = COPY [[XORI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s64) = COPY $f10_d
%1:fprb(s64) = COPY $f11_d
%4:gprb(s32) = G_FCMP floatpred(ueq), %0(s64), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_ugt_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_d, $f11_d
; CHECK-LABEL: name: fcmp_ugt_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[FLE_D:%[0-9]+]]:gpr = FLE_D [[COPY]], [[COPY1]]
; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLE_D]], 1
; CHECK-NEXT: $x10 = COPY [[XORI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s64) = COPY $f10_d
%1:fprb(s64) = COPY $f11_d
%4:gprb(s32) = G_FCMP floatpred(ugt), %0(s64), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_uge_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_d, $f11_d
; CHECK-LABEL: name: fcmp_uge_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[FLT_D:%[0-9]+]]:gpr = FLT_D [[COPY]], [[COPY1]]
; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLT_D]], 1
; CHECK-NEXT: $x10 = COPY [[XORI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s64) = COPY $f10_d
%1:fprb(s64) = COPY $f11_d
%4:gprb(s32) = G_FCMP floatpred(uge), %0(s64), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_ult_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_d, $f11_d
; CHECK-LABEL: name: fcmp_ult_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[FLE_D:%[0-9]+]]:gpr = FLE_D [[COPY1]], [[COPY]]
; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLE_D]], 1
; CHECK-NEXT: $x10 = COPY [[XORI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s64) = COPY $f10_d
%1:fprb(s64) = COPY $f11_d
%4:gprb(s32) = G_FCMP floatpred(ult), %0(s64), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_ule_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_d, $f11_d
; CHECK-LABEL: name: fcmp_ule_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[FLT_D:%[0-9]+]]:gpr = FLT_D [[COPY1]], [[COPY]]
; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLT_D]], 1
; CHECK-NEXT: $x10 = COPY [[XORI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s64) = COPY $f10_d
%1:fprb(s64) = COPY $f11_d
%4:gprb(s32) = G_FCMP floatpred(ule), %0(s64), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_une_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_d, $f11_d
; CHECK-LABEL: name: fcmp_une_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[FEQ_D:%[0-9]+]]:gpr = FEQ_D [[COPY]], [[COPY1]]
; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FEQ_D]], 1
; CHECK-NEXT: $x10 = COPY [[XORI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s64) = COPY $f10_d
%1:fprb(s64) = COPY $f11_d
%4:gprb(s32) = G_FCMP floatpred(une), %0(s64), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
---
name: fcmp_uno_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $f10_d, $f11_d
; CHECK-LABEL: name: fcmp_uno_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[FEQ_D:%[0-9]+]]:gpr = FEQ_D [[COPY]], [[COPY]]
; CHECK-NEXT: [[FEQ_D1:%[0-9]+]]:gpr = FEQ_D [[COPY1]], [[COPY1]]
; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[FEQ_D]], [[FEQ_D1]]
; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[AND]], 1
; CHECK-NEXT: $x10 = COPY [[XORI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:fprb(s64) = COPY $f10_d
%1:fprb(s64) = COPY $f11_d
%4:gprb(s32) = G_FCMP floatpred(uno), %0(s64), %1
$x10 = COPY %4(s32)
PseudoRET implicit $x10
...
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