llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \
# RUN:   -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir \
# RUN:   -verify-machineinstrs %s -o - | FileCheck %s

---
name:            test_trap
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: test_trap
    ; CHECK: UNIMP
    ; CHECK-NEXT: PseudoRET
    G_TRAP
    PseudoRET

...
---
name:            test_debugtrap
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: test_debugtrap
    ; CHECK: EBREAK
    ; CHECK-NEXT: PseudoRET
    G_DEBUGTRAP
    PseudoRET

...