alu_m-rv32.mir | Explore in Territory

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV32I %s

---
name:            mul_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: mul_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[MUL]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = G_MUL %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            sdiv_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: sdiv_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[DIV:%[0-9]+]]:gpr = DIV [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[DIV]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = G_SDIV %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            srem_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: srem_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[REM:%[0-9]+]]:gpr = REM [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[REM]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = G_SREM %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            smulh_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: smulh_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[MULH:%[0-9]+]]:gpr = MULH [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[MULH]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = G_SMULH %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            udiv_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: udiv_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[DIVU:%[0-9]+]]:gpr = DIVU [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[DIVU]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = G_UDIV %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            urem_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: urem_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[REMU:%[0-9]+]]:gpr = REMU [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[REMU]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = G_UREM %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            mul_i64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11, $x12, $x13

    ; RV32I-LABEL: name: mul_i64
    ; RV32I: liveins: $x10, $x11, $x12, $x13
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
    ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13
    ; RV32I-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY2]]
    ; RV32I-NEXT: [[MUL1:%[0-9]+]]:gpr = MUL [[COPY1]], [[COPY2]]
    ; RV32I-NEXT: [[MUL2:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY3]]
    ; RV32I-NEXT: [[MULHU:%[0-9]+]]:gpr = MULHU [[COPY]], [[COPY2]]
    ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[MUL1]], [[MUL2]]
    ; RV32I-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[ADD]], [[MULHU]]
    ; RV32I-NEXT: $x10 = COPY [[MUL]]
    ; RV32I-NEXT: $x11 = COPY [[ADD1]]
    ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = COPY $x12
    %3:gprb(s32) = COPY $x13
    %4:gprb(s32) = G_MUL %0, %2
    %5:gprb(s32) = G_MUL %1, %2
    %6:gprb(s32) = G_MUL %0, %3
    %7:gprb(s32) = G_UMULH %0, %2
    %8:gprb(s32) = G_ADD %5, %6
    %9:gprb(s32) = G_ADD %8, %7
    $x10 = COPY %4(s32)
    $x11 = COPY %9(s32)
    PseudoRET implicit $x10, implicit $x11

...
llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv32.mir
