llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \
# RUN: -verify-machineinstrs %s -o - | FileCheck %s

---
name:            ptrtoint_s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; CHECK-LABEL: name: ptrtoint_s32
    ; CHECK: liveins: $x10, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: $x10 = COPY [[COPY]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(p0) = COPY $x10
    %1:gprb(s32) = G_PTRTOINT %0(p0)
    $x10 = COPY %1(s32)
    PseudoRET implicit $x10

...
---
name:            inttoptr_s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; CHECK-LABEL: name: inttoptr_s32
    ; CHECK: liveins: $x10, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: $x10 = COPY [[COPY]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(p0) = G_INTTOPTR %0(s32)
    $x10 = COPY %1(p0)
    PseudoRET implicit $x10

...