load-rv32.mir | Explore in Territory

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
# RUN: | FileCheck %s

--- |
  define void @load_i8(ptr %addr) { ret void }
  define void @load_i16(ptr %addr) { ret void }
  define void @load_i32(ptr %addr) { ret void }
  define void @zextload_i8(ptr %addr) { ret void }
  define void @zextload_i16(ptr %addr) { ret void }
  define void @sextload_i8(ptr %addr) { ret void }
  define void @sextload_i16(ptr %addr) { ret void }
  define void @load_p0(ptr %addr) { ret void }
  define void @load_fi_i32() {
    %ptr0 = alloca i32
    ret void
  }
  define void @load_fi_gep_i32() {
    %ptr0 = alloca [2 x i32]
    ret void
  }
  define void @load_gep_i32(ptr %addr) { ret void }
...
---
name:            load_i8
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: load_i8
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[LBU:%[0-9]+]]:gpr = LBU [[COPY]], 0 :: (load (s8))
    ; CHECK-NEXT: $x10 = COPY [[LBU]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(p0) = COPY $x10
    %1:gprb(s32) = G_LOAD %0(p0) :: (load (s8))
    $x10 = COPY %1(s32)
    PseudoRET implicit $x10

...
---
name:            load_i16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: load_i16
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16))
    ; CHECK-NEXT: $x10 = COPY [[LH]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(p0) = COPY $x10
    %1:gprb(s32) = G_LOAD %0(p0) :: (load (s16))
    $x10 = COPY %1(s32)
    PseudoRET implicit $x10

...
---
name:            load_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: load_i32
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))
    ; CHECK-NEXT: $x10 = COPY [[LW]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(p0) = COPY $x10
    %1:gprb(s32) = G_LOAD %0(p0) :: (load (s32))
    $x10 = COPY %1(s32)
    PseudoRET implicit $x10

...
---
name:            zextload_i8
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: zextload_i8
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[LBU:%[0-9]+]]:gpr = LBU [[COPY]], 0 :: (load (s8))
    ; CHECK-NEXT: $x10 = COPY [[LBU]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(p0) = COPY $x10
    %1:gprb(s32) = G_ZEXTLOAD %0(p0) :: (load (s8))
    $x10 = COPY %1(s32)
    PseudoRET implicit $x10

...
---
name:            zextload_i16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: zextload_i16
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[LHU:%[0-9]+]]:gpr = LHU [[COPY]], 0 :: (load (s16))
    ; CHECK-NEXT: $x10 = COPY [[LHU]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(p0) = COPY $x10
    %1:gprb(s32) = G_ZEXTLOAD %0(p0) :: (load (s16))
    $x10 = COPY %1(s32)
    PseudoRET implicit $x10

...
---
name:            sextload_i8
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: sextload_i8
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[LB:%[0-9]+]]:gpr = LB [[COPY]], 0 :: (load (s8))
    ; CHECK-NEXT: $x10 = COPY [[LB]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(p0) = COPY $x10
    %1:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s8))
    $x10 = COPY %1(s32)
    PseudoRET implicit $x10

...
---
name:            sextload_i16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: sextload_i16
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16))
    ; CHECK-NEXT: $x10 = COPY [[LH]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(p0) = COPY $x10
    %1:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s16))
    $x10 = COPY %1(s32)
    PseudoRET implicit $x10

...
---
name:            load_p0
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: load_p0
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (p0))
    ; CHECK-NEXT: $x10 = COPY [[LW]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(p0) = COPY $x10
    %1:gprb(p0) = G_LOAD %0(p0) :: (load (p0))
    $x10 = COPY %1(p0)
    PseudoRET implicit $x10

...
---
name:            load_fi_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true

stack:
  - { id: 0, name: ptr0, offset: 0, size: 4, alignment: 4 }

body:            |
  bb.0:
    ; CHECK-LABEL: name: load_fi_i32
    ; CHECK: [[LW:%[0-9]+]]:gpr = LW %stack.0.ptr0, 0 :: (load (s32))
    ; CHECK-NEXT: $x10 = COPY [[LW]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
    %1:gprb(s32) = G_LOAD %0(p0) :: (load (s32))
    $x10 = COPY %1(s32)
    PseudoRET implicit $x10

...
---
name:            load_fi_gep_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true

stack:
  - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 4 }

body:            |
  bb.0:
    ; CHECK-LABEL: name: load_fi_gep_i32
    ; CHECK: [[LW:%[0-9]+]]:gpr = LW %stack.0.ptr0, 4 :: (load (s32))
    ; CHECK-NEXT: $x10 = COPY [[LW]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
    %1:gprb(s32) = G_CONSTANT i32 4
    %2:gprb(p0) = G_PTR_ADD %0(p0), %1(s32)
    %3:gprb(s32) = G_LOAD %2(p0) :: (load (s32))
    $x10 = COPY %3(s32)
    PseudoRET implicit $x10

...
---
name:            load_gep_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: load_gep_i32
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32))
    ; CHECK-NEXT: $x10 = COPY [[LW]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(p0) = COPY $x10
    %1:gprb(s32) = G_CONSTANT i32 4
    %2:gprb(p0) = G_PTR_ADD %0(p0), %1(s32)
    %3:gprb(s32) = G_LOAD %2(p0) :: (load (s32))
    $x10 = COPY %3(s32)
    PseudoRET implicit $x10

...
llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
