alu-rv32.mir | Explore in Territory

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV32I %s

---
name:            add_i8_signext
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: add_i8_signext
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
    ; RV32I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADD]], 24
    ; RV32I-NEXT: [[SRAI:%[0-9]+]]:gpr = SRAI [[SLLI]], 24
    ; RV32I-NEXT: $x10 = COPY [[SRAI]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = G_ADD %0, %1
    %3:gprb(s32) = G_CONSTANT i32 24
    %4:gprb(s32) = G_SHL %2, %3(s32)
    %5:gprb(s32) = G_ASHR %4, %3(s32)
    $x10 = COPY %5(s32)
    PseudoRET implicit $x10

...
---
name:            add_i8_zeroext
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: add_i8_zeroext
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
    ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[ADD]], 255
    ; RV32I-NEXT: $x10 = COPY [[ANDI]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = G_ADD %0, %1
    %3:gprb(s32) = G_CONSTANT i32 255
    %4:gprb(s32) = G_AND %2, %3
    $x10 = COPY %4(s32)
    PseudoRET implicit $x10

...
---
name:            add_i16_signext
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: add_i16_signext
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
    ; RV32I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADD]], 16
    ; RV32I-NEXT: [[SRAI:%[0-9]+]]:gpr = SRAI [[SLLI]], 16
    ; RV32I-NEXT: $x10 = COPY [[SRAI]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = G_ADD %0, %1
    %3:gprb(s32) = G_CONSTANT i32 16
    %4:gprb(s32) = G_SHL %2, %3(s32)
    %5:gprb(s32) = G_ASHR %4, %3(s32)
    $x10 = COPY %5(s32)
    PseudoRET implicit $x10

...
---
name:            add_i16_zeroext
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: add_i16_zeroext
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
    ; RV32I-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 16
    ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], -1
    ; RV32I-NEXT: [[AND:%[0-9]+]]:gpr = AND [[ADD]], [[ADDI]]
    ; RV32I-NEXT: $x10 = COPY [[AND]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = G_ADD %0, %1
    %3:gprb(s32) = G_CONSTANT i32 65535
    %4:gprb(s32) = G_AND %2, %3
    $x10 = COPY %4(s32)
    PseudoRET implicit $x10

...
---
name:            add_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: add_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[ADD]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = G_ADD %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            addi_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10

    ; RV32I-LABEL: name: addi_i32
    ; RV32I: liveins: $x10
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 1234
    ; RV32I-NEXT: $x10 = COPY [[ADDI]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = G_CONSTANT i32 1234
    %2:gprb(s32) = G_ADD %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            sub_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: sub_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[SUB]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = G_SUB %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            subi_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10

    ; RV32I-LABEL: name: subi_i32
    ; RV32I: liveins: $x10
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 1234
    ; RV32I-NEXT: $x10 = COPY [[ADDI]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = G_CONSTANT i32 -1234
    %2:gprb(s32) = G_SUB %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            sll_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: sll_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[SLL]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = G_SHL %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            slli_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10

    ; RV32I-LABEL: name: slli_i32
    ; RV32I: liveins: $x10
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 31
    ; RV32I-NEXT: $x10 = COPY [[SLLI]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = G_CONSTANT i32 31
    %2:gprb(s32) = G_SHL %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            sra_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: sra_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[SRA:%[0-9]+]]:gpr = SRA [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[SRA]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = G_ASHR %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            srai_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10

    ; RV32I-LABEL: name: srai_i32
    ; RV32I: liveins: $x10
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[SRAI:%[0-9]+]]:gpr = SRAI [[COPY]], 31
    ; RV32I-NEXT: $x10 = COPY [[SRAI]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = G_CONSTANT i32 31
    %2:gprb(s32) = G_ASHR %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            srl_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: srl_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[SRL]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = G_LSHR %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            srli_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10

    ; RV32I-LABEL: name: srli_i32
    ; RV32I: liveins: $x10
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[COPY]], 31
    ; RV32I-NEXT: $x10 = COPY [[SRLI]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = G_CONSTANT i32 31
    %2:gprb(s32) = G_LSHR %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            and_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: and_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[AND:%[0-9]+]]:gpr = AND [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[AND]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = G_AND %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            andi_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10

    ; RV32I-LABEL: name: andi_i32
    ; RV32I: liveins: $x10
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1234
    ; RV32I-NEXT: $x10 = COPY [[ANDI]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = G_CONSTANT i32 1234
    %2:gprb(s32) = G_AND %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            or_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: or_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[OR:%[0-9]+]]:gpr = OR [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[OR]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = G_OR %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            ori_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10

    ; RV32I-LABEL: name: ori_i32
    ; RV32I: liveins: $x10
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[ORI:%[0-9]+]]:gpr = ORI [[COPY]], 1234
    ; RV32I-NEXT: $x10 = COPY [[ORI]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = G_CONSTANT i32 1234
    %2:gprb(s32) = G_OR %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            xor_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: xor_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[XOR]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = G_XOR %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            xori_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10

    ; RV32I-LABEL: name: xori_i32
    ; RV32I: liveins: $x10
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[COPY]], 1234
    ; RV32I-NEXT: $x10 = COPY [[XORI]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = G_CONSTANT i32 1234
    %2:gprb(s32) = G_XOR %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            add_i64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11, $x12, $x13

    ; RV32I-LABEL: name: add_i64
    ; RV32I: liveins: $x10, $x11, $x12, $x13
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
    ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13
    ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY2]]
    ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADD]], [[COPY2]]
    ; RV32I-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[COPY1]], [[COPY3]]
    ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[SLTU]], 1
    ; RV32I-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[ADD1]], [[ANDI]]
    ; RV32I-NEXT: $x10 = COPY [[ADD]]
    ; RV32I-NEXT: $x11 = COPY [[ADD2]]
    ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = COPY $x12
    %3:gprb(s32) = COPY $x13
    %4:gprb(s32) = G_ADD %0, %2
    %5:gprb(s32) = G_ICMP intpred(ult), %4(s32), %2
    %6:gprb(s32) = G_ADD %1, %3
    %7:gprb(s32) = G_CONSTANT i32 1
    %8:gprb(s32) = G_AND %5, %7
    %9:gprb(s32) = G_ADD %6, %8
    $x10 = COPY %4(s32)
    $x11 = COPY %9(s32)
    PseudoRET implicit $x10, implicit $x11

...
---
name:            sub_i64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11, $x12, $x13

    ; RV32I-LABEL: name: sub_i64
    ; RV32I: liveins: $x10, $x11, $x12, $x13
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
    ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13
    ; RV32I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[COPY2]]
    ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY2]]
    ; RV32I-NEXT: [[SUB1:%[0-9]+]]:gpr = SUB [[COPY1]], [[COPY3]]
    ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[SLTU]], 1
    ; RV32I-NEXT: [[SUB2:%[0-9]+]]:gpr = SUB [[SUB1]], [[ANDI]]
    ; RV32I-NEXT: $x10 = COPY [[SUB]]
    ; RV32I-NEXT: $x11 = COPY [[SUB2]]
    ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = COPY $x12
    %3:gprb(s32) = COPY $x13
    %4:gprb(s32) = G_SUB %0, %2
    %5:gprb(s32) = G_ICMP intpred(ult), %0(s32), %2
    %6:gprb(s32) = G_SUB %1, %3
    %7:gprb(s32) = G_CONSTANT i32 1
    %8:gprb(s32) = G_AND %5, %7
    %9:gprb(s32) = G_SUB %6, %8
    $x10 = COPY %4(s32)
    $x11 = COPY %9(s32)
    PseudoRET implicit $x10, implicit $x11

...
llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
