fcmp-f16-rv32.mir | Explore in Territory

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \
# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s

---
name:            fcmp_oeq_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fcmp_oeq_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FEQ_H:%[0-9]+]]:gpr = nofpexcept FEQ_H [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $x10 = COPY [[FEQ_H]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %4:gprb(s32) = G_FCMP floatpred(oeq), %0(s16), %1
    $x10 = COPY %4(s32)
    PseudoRET implicit $x10

...
---
name:            fcmp_ogt_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fcmp_ogt_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY1]], [[COPY]]
    ; CHECK-NEXT: $x10 = COPY [[FLT_H]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %4:gprb(s32) = G_FCMP floatpred(ogt), %0(s16), %1
    $x10 = COPY %4(s32)
    PseudoRET implicit $x10

...
---
name:            fcmp_oge_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fcmp_oge_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FLE_H:%[0-9]+]]:gpr = FLE_H [[COPY1]], [[COPY]]
    ; CHECK-NEXT: $x10 = COPY [[FLE_H]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %4:gprb(s32) = G_FCMP floatpred(oge), %0(s16), %1
    $x10 = COPY %4(s32)
    PseudoRET implicit $x10

...
---
name:            fcmp_olt_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fcmp_olt_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = nofpexcept FLT_H [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $x10 = COPY [[FLT_H]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %4:gprb(s32) = G_FCMP floatpred(olt), %0(s16), %1
    $x10 = COPY %4(s32)
    PseudoRET implicit $x10

...
---
name:            fcmp_ole_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fcmp_ole_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FLE_H:%[0-9]+]]:gpr = nofpexcept FLE_H [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $x10 = COPY [[FLE_H]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %4:gprb(s32) = G_FCMP floatpred(ole), %0(s16), %1
    $x10 = COPY %4(s32)
    PseudoRET implicit $x10

...
---
name:            fcmp_one_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fcmp_one_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[FLT_H1:%[0-9]+]]:gpr = FLT_H [[COPY1]], [[COPY]]
    ; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_H]], [[FLT_H1]]
    ; CHECK-NEXT: $x10 = COPY [[OR]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %4:gprb(s32) = G_FCMP floatpred(one), %0(s16), %1
    $x10 = COPY %4(s32)
    PseudoRET implicit $x10

...
---
name:            fcmp_ord_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fcmp_ord_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FEQ_H:%[0-9]+]]:gpr = FEQ_H [[COPY]], [[COPY]]
    ; CHECK-NEXT: [[FEQ_H1:%[0-9]+]]:gpr = FEQ_H [[COPY1]], [[COPY1]]
    ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[FEQ_H]], [[FEQ_H1]]
    ; CHECK-NEXT: $x10 = COPY [[AND]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %4:gprb(s32) = G_FCMP floatpred(ord), %0(s16), %1
    $x10 = COPY %4(s32)
    PseudoRET implicit $x10

...
---
name:            fcmp_ueq_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fcmp_ueq_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[FLT_H1:%[0-9]+]]:gpr = FLT_H [[COPY1]], [[COPY]]
    ; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_H]], [[FLT_H1]]
    ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[OR]], 1
    ; CHECK-NEXT: $x10 = COPY [[XORI]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %4:gprb(s32) = G_FCMP floatpred(ueq), %0(s16), %1
    $x10 = COPY %4(s32)
    PseudoRET implicit $x10

...
---
name:            fcmp_ugt_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fcmp_ugt_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FLE_H:%[0-9]+]]:gpr = FLE_H [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLE_H]], 1
    ; CHECK-NEXT: $x10 = COPY [[XORI]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %4:gprb(s32) = G_FCMP floatpred(ugt), %0(s16), %1
    $x10 = COPY %4(s32)
    PseudoRET implicit $x10

...
---
name:            fcmp_uge_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fcmp_uge_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLT_H]], 1
    ; CHECK-NEXT: $x10 = COPY [[XORI]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %4:gprb(s32) = G_FCMP floatpred(uge), %0(s16), %1
    $x10 = COPY %4(s32)
    PseudoRET implicit $x10

...
---
name:            fcmp_ult_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fcmp_ult_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FLE_H:%[0-9]+]]:gpr = FLE_H [[COPY1]], [[COPY]]
    ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLE_H]], 1
    ; CHECK-NEXT: $x10 = COPY [[XORI]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %4:gprb(s32) = G_FCMP floatpred(ult), %0(s16), %1
    $x10 = COPY %4(s32)
    PseudoRET implicit $x10

...
---
name:            fcmp_ule_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fcmp_ule_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY1]], [[COPY]]
    ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLT_H]], 1
    ; CHECK-NEXT: $x10 = COPY [[XORI]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %4:gprb(s32) = G_FCMP floatpred(ule), %0(s16), %1
    $x10 = COPY %4(s32)
    PseudoRET implicit $x10

...
---
name:            fcmp_une_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fcmp_une_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FEQ_H:%[0-9]+]]:gpr = FEQ_H [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FEQ_H]], 1
    ; CHECK-NEXT: $x10 = COPY [[XORI]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %4:gprb(s32) = G_FCMP floatpred(une), %0(s16), %1
    $x10 = COPY %4(s32)
    PseudoRET implicit $x10

...
---
name:            fcmp_uno_f16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fcmp_uno_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
    ; CHECK-NEXT: [[FEQ_H:%[0-9]+]]:gpr = FEQ_H [[COPY]], [[COPY]]
    ; CHECK-NEXT: [[FEQ_H1:%[0-9]+]]:gpr = FEQ_H [[COPY1]], [[COPY1]]
    ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[FEQ_H]], [[FEQ_H1]]
    ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[AND]], 1
    ; CHECK-NEXT: $x10 = COPY [[XORI]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s16) = COPY $f10_h
    %1:fprb(s16) = COPY $f11_h
    %4:gprb(s32) = G_FCMP floatpred(uno), %0(s16), %1
    $x10 = COPY %4(s32)
    PseudoRET implicit $x10

...
llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv32.mir
