llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \
# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=instruction-select \
# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s

---
name:            bswap_s32
legalized:       true
regBankSelected: true
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: bswap_s32
    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[REV8_RV32_:%[0-9]+]]:gpr = REV8_RV32 [[COPY]]
    ; CHECK-NEXT: $x10 = COPY [[REV8_RV32_]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = G_BSWAP %0
    $x10 = COPY %1(s32)
    PseudoRET implicit $x10

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