legalize-splatvector-rv32.mir | Explore in Territory

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s

---
name:            splatvector_nxv1i1_0
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv1i1_0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMCLR_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 1 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s1) = G_CONSTANT i1 0
    %1:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR %0(s1)
    $v0 = COPY %1(<vscale x 1 x s1>)
    PseudoRET implicit $v0

...
---
name:            splatvector_nxv1i1_1
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv1i1_1
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 1 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s1) = G_CONSTANT i1 1
    %1:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR %0(s1)
    $v0 = COPY %1(<vscale x 1 x s1>)
    PseudoRET implicit $v0

...
---
name:            splatvector_nxv1i1_2
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x10

    ; CHECK-LABEL: name: splatvector_nxv1i1_2
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[AND1]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C1]](s32)
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 1 x s8>), [[SPLAT_VECTOR1]]
    ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 1 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s32) = COPY $x10
    %1:_(s1) = G_TRUNC %0(s32)
    %2:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR %1(s1)
    $v0 = COPY %2(<vscale x 1 x s1>)
    PseudoRET implicit $v0
...
---
name:            splatvector_nxv2i1_0
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv2i1_0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMCLR_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 2 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s1) = G_CONSTANT i1 0
    %1:_(<vscale x 2 x s1>) = G_SPLAT_VECTOR %0(s1)
    $v0 = COPY %1(<vscale x 2 x s1>)
    PseudoRET implicit $v0

...
---
name:            splatvector_nxv2i1_1
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv2i1_1
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 2 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s1) = G_CONSTANT i1 1
    %1:_(<vscale x 2 x s1>) = G_SPLAT_VECTOR %0(s1)
    $v0 = COPY %1(<vscale x 2 x s1>)
    PseudoRET implicit $v0

...
---
name:            splatvector_nxv2i1_2
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x10

    ; CHECK-LABEL: name: splatvector_nxv2i1_2
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[AND1]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C1]](s32)
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 2 x s8>), [[SPLAT_VECTOR1]]
    ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 2 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s32) = COPY $x10
    %1:_(s1) = G_TRUNC %0(s32)
    %2:_(<vscale x 2 x s1>) = G_SPLAT_VECTOR %1(s1)
    $v0 = COPY %2(<vscale x 2 x s1>)
    PseudoRET implicit $v0
...
---
name:            splatvector_nxv4i1_0
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv4i1_0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMCLR_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 4 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s1) = G_CONSTANT i1 0
    %1:_(<vscale x 4 x s1>) = G_SPLAT_VECTOR %0(s1)
    $v0 = COPY %1(<vscale x 4 x s1>)
    PseudoRET implicit $v0

...
---
name:            splatvector_nxv4i1_1
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv4i1_1
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 4 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s1) = G_CONSTANT i1 1
    %1:_(<vscale x 4 x s1>) = G_SPLAT_VECTOR %0(s1)
    $v0 = COPY %1(<vscale x 4 x s1>)
    PseudoRET implicit $v0

...
---
name:            splatvector_nxv4i1_2
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x10

    ; CHECK-LABEL: name: splatvector_nxv4i1_2
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[AND1]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C1]](s32)
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 4 x s8>), [[SPLAT_VECTOR1]]
    ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 4 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s32) = COPY $x10
    %1:_(s1) = G_TRUNC %0(s32)
    %2:_(<vscale x 4 x s1>) = G_SPLAT_VECTOR %1(s1)
    $v0 = COPY %2(<vscale x 4 x s1>)
    PseudoRET implicit $v0
...
---
name:            splatvector_nxv8i1_0
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv8i1_0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMCLR_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 8 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s1) = G_CONSTANT i1 0
    %1:_(<vscale x 8 x s1>) = G_SPLAT_VECTOR %0(s1)
    $v0 = COPY %1(<vscale x 8 x s1>)
    PseudoRET implicit $v0

...
---
name:            splatvector_nxv8i1_1
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv8i1_1
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 8 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s1) = G_CONSTANT i1 1
    %1:_(<vscale x 8 x s1>) = G_SPLAT_VECTOR %0(s1)
    $v0 = COPY %1(<vscale x 8 x s1>)
    PseudoRET implicit $v0

...
---
name:            splatvector_nxv8i1_2
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x10

    ; CHECK-LABEL: name: splatvector_nxv8i1_2
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[AND1]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C1]](s32)
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 8 x s8>), [[SPLAT_VECTOR1]]
    ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 8 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s32) = COPY $x10
    %1:_(s1) = G_TRUNC %0(s32)
    %2:_(<vscale x 8 x s1>) = G_SPLAT_VECTOR %1(s1)
    $v0 = COPY %2(<vscale x 8 x s1>)
    PseudoRET implicit $v0
...
---
name:            splatvector_nxv16i1_0
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv16i1_0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMCLR_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 16 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s1) = G_CONSTANT i1 0
    %1:_(<vscale x 16 x s1>) = G_SPLAT_VECTOR %0(s1)
    $v0 = COPY %1(<vscale x 16 x s1>)
    PseudoRET implicit $v0

...
---
name:            splatvector_nxv16i1_1
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv16i1_1
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 16 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s1) = G_CONSTANT i1 1
    %1:_(<vscale x 16 x s1>) = G_SPLAT_VECTOR %0(s1)
    $v0 = COPY %1(<vscale x 16 x s1>)
    PseudoRET implicit $v0

...
---
name:            splatvector_nxv16i1_2
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x10

    ; CHECK-LABEL: name: splatvector_nxv16i1_2
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[AND1]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C1]](s32)
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 16 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 16 x s8>), [[SPLAT_VECTOR1]]
    ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 16 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s32) = COPY $x10
    %1:_(s1) = G_TRUNC %0(s32)
    %2:_(<vscale x 16 x s1>) = G_SPLAT_VECTOR %1(s1)
    $v0 = COPY %2(<vscale x 16 x s1>)
    PseudoRET implicit $v0
...
---
name:            splatvector_nxv32i1_0
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv32i1_0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMCLR_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 32 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s1) = G_CONSTANT i1 0
    %1:_(<vscale x 32 x s1>) = G_SPLAT_VECTOR %0(s1)
    $v0 = COPY %1(<vscale x 32 x s1>)
    PseudoRET implicit $v0

...
---
name:            splatvector_nxv32i1_1
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv32i1_1
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 32 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s1) = G_CONSTANT i1 1
    %1:_(<vscale x 32 x s1>) = G_SPLAT_VECTOR %0(s1)
    $v0 = COPY %1(<vscale x 32 x s1>)
    PseudoRET implicit $v0

...
---
name:            splatvector_nxv32i1_2
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x10

    ; CHECK-LABEL: name: splatvector_nxv32i1_2
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[AND1]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[C1]](s32)
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 32 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 32 x s8>), [[SPLAT_VECTOR1]]
    ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 32 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s32) = COPY $x10
    %1:_(s1) = G_TRUNC %0(s32)
    %2:_(<vscale x 32 x s1>) = G_SPLAT_VECTOR %1(s1)
    $v0 = COPY %2(<vscale x 32 x s1>)
    PseudoRET implicit $v0
...
---
name:            splatvector_nxv64i1_0
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv64i1_0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMCLR_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 64 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s1) = G_CONSTANT i1 0
    %1:_(<vscale x 64 x s1>) = G_SPLAT_VECTOR %0(s1)
    $v0 = COPY %1(<vscale x 64 x s1>)
    PseudoRET implicit $v0

...
---
name:            splatvector_nxv64i1_1
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv64i1_1
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 64 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s1) = G_CONSTANT i1 1
    %1:_(<vscale x 64 x s1>) = G_SPLAT_VECTOR %0(s1)
    $v0 = COPY %1(<vscale x 64 x s1>)
    PseudoRET implicit $v0

...
---
name:            splatvector_nxv64i1_2
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x10

    ; CHECK-LABEL: name: splatvector_nxv64i1_2
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[AND1]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C1]](s32)
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 64 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 64 x s8>), [[SPLAT_VECTOR1]]
    ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 64 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s32) = COPY $x10
    %1:_(s1) = G_TRUNC %0(s32)
    %2:_(<vscale x 64 x s1>) = G_SPLAT_VECTOR %1(s1)
    $v0 = COPY %2(<vscale x 64 x s1>)
    PseudoRET implicit $v0
...

---
name:            splatvector_nxv1i8
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv1i8
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C]](s32)
    ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s8>)
    ; CHECK-NEXT: PseudoRET implicit $v8
    %1:_(s8) = G_CONSTANT i8 0
    %2:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR %1(s8)
    $v8 = COPY %2(<vscale x 1 x s8>)
    PseudoRET implicit $v8

...

---
name:            splatvector_nxv2i8
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv2i8
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C]](s32)
    ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s8>)
    ; CHECK-NEXT: PseudoRET implicit $v8
    %1:_(s8) = G_CONSTANT i8 0
    %2:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR %1(s8)
    $v8 = COPY %2(<vscale x 2 x s8>)
    PseudoRET implicit $v8

...
---
name:            splatvector_nxv4i8
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv4i8
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C]](s32)
    ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s8>)
    ; CHECK-NEXT: PseudoRET implicit $v8
    %1:_(s8) = G_CONSTANT i8 0
    %2:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR %1(s8)
    $v8 = COPY %2(<vscale x 4 x s8>)
    PseudoRET implicit $v8

...
---
name:            splatvector_nxv8i8
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv8i8
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C]](s32)
    ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s8>)
    ; CHECK-NEXT: PseudoRET implicit $v8
    %1:_(s8) = G_CONSTANT i8 0
    %2:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR %1(s8)
    $v8 = COPY %2(<vscale x 8 x s8>)
    PseudoRET implicit $v8

...
---
name:            splatvector_nxv16i8
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv16i8
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C]](s32)
    ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s8>)
    ; CHECK-NEXT: PseudoRET implicit $v8m2
    %1:_(s8) = G_CONSTANT i8 0
    %2:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR %1(s8)
    $v8m2 = COPY %2(<vscale x 16 x s8>)
    PseudoRET implicit $v8m2

...
---
name:            splatvector_nxv1i16
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv1i16
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[C]](s32)
    ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s16>)
    ; CHECK-NEXT: PseudoRET implicit $v8
    %1:_(s16) = G_CONSTANT i16 0
    %2:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR %1(s16)
    $v8 = COPY %2(<vscale x 1 x s16>)
    PseudoRET implicit $v8

...
---
name:            splatvector_nxv2i16
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv2i16
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[C]](s32)
    ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s16>)
    ; CHECK-NEXT: PseudoRET implicit $v8
    %1:_(s16) = G_CONSTANT i16 0
    %2:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR %1(s16)
    $v8 = COPY %2(<vscale x 2 x s16>)
    PseudoRET implicit $v8

...
---
name:            splatvector_nxv4i16
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv4i16
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[C]](s32)
    ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s16>)
    ; CHECK-NEXT: PseudoRET implicit $v8
    %1:_(s16) = G_CONSTANT i16 0
    %2:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR %1(s16)
    $v8 = COPY %2(<vscale x 4 x s16>)
    PseudoRET implicit $v8

...
---
name:            splatvector_nxv8i16
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv8i16
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[C]](s32)
    ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s16>)
    ; CHECK-NEXT: PseudoRET implicit $v8m2
    %1:_(s16) = G_CONSTANT i16 0
    %2:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR %1(s16)
    $v8m2 = COPY %2(<vscale x 8 x s16>)
    PseudoRET implicit $v8m2

...
---
name:            splatvector_nxv16i16
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv16i16
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[C]](s32)
    ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s16>)
    ; CHECK-NEXT: PseudoRET implicit $v8m4
    %1:_(s16) = G_CONSTANT i16 0
    %2:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR %1(s16)
    $v8m4 = COPY %2(<vscale x 16 x s16>)
    PseudoRET implicit $v8m4

...
---
name:            splatvector_nxv1i32
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv1i32
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[C]](s32)
    ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s32>)
    ; CHECK-NEXT: PseudoRET implicit $v8
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR %1(s32)
    $v8 = COPY %2(<vscale x 1 x s32>)
    PseudoRET implicit $v8

...
---
name:            splatvector_nxv2i32
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv2i32
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[C]](s32)
    ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s32>)
    ; CHECK-NEXT: PseudoRET implicit $v8
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR %1(s32)
    $v8 = COPY %2(<vscale x 2 x s32>)
    PseudoRET implicit $v8

...
---
name:            splatvector_nxv4i32
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv4i32
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[C]](s32)
    ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s32>)
    ; CHECK-NEXT: PseudoRET implicit $v8m2
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %1(s32)
    $v8m2 = COPY %2(<vscale x 4 x s32>)
    PseudoRET implicit $v8m2

...
---
name:            splatvector_nxv8i32
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv8i32
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[C]](s32)
    ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s32>)
    ; CHECK-NEXT: PseudoRET implicit $v8m4
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR %1(s32)
    $v8m4 = COPY %2(<vscale x 8 x s32>)
    PseudoRET implicit $v8m4

...
---
name:            splatvector_nxv16i32
legalized:       false
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splatvector_nxv16i32
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[C]](s32)
    ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s32>)
    ; CHECK-NEXT: PseudoRET implicit $v8m8
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR %1(s32)
    $v8m8 = COPY %2(<vscale x 16 x s32>)
    PseudoRET implicit $v8m8

...
llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv32.mir
