llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-select-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s

---
name:            select_f64
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x10, $f10_d, $f11_d

    ; CHECK-LABEL: name: select_f64
    ; CHECK: liveins: $x10, $f10_d, $f11_d
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f10_d
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $f11_d
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
    ; CHECK-NEXT: $f10_d = COPY [[SELECT]](s64)
    ; CHECK-NEXT: PseudoRET implicit $f10_d
    %3:_(s32) = COPY $x10
    %0:_(s1) = G_TRUNC %3(s32)
    %1:_(s64) = COPY $f10_d
    %2:_(s64) = COPY $f11_d
    %4:_(s64) = G_SELECT %0(s1), %1, %2
    $f10_d = COPY %4(s64)
    PseudoRET implicit $f10_d

...