legalize-extload-rv32.mir | Explore in Territory

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s

---
name:            zextload_i8_i16
body:             |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: zextload_i8_i16
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
    ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(p0) = COPY $x10
    %2:_(s16) = G_ZEXTLOAD %0(p0) :: (load (s8))
    %3:_(s32) = G_ANYEXT %2(s16)
    $x10 = COPY %3(s32)
    PseudoRET implicit $x10

...
---
name:            zextload_i8_i32
body:             |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: zextload_i8_i32
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
    ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(p0) = COPY $x10
    %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8))
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            zextload_i16_i32
body:             |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: zextload_i16_i32
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
    ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(p0) = COPY $x10
    %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16))
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            zextload_i8_i64
body:             |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: zextload_i8_i64
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)
    ; CHECK-NEXT: $x11 = COPY [[C]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
    %0:_(p0) = COPY $x10
    %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s8))
    %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
    $x10 = COPY %3(s32)
    $x11 = COPY %4(s32)
    PseudoRET implicit $x10, implicit $x11

...
---
name:            zextload_i16_i64
body:             |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: zextload_i16_i64
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)
    ; CHECK-NEXT: $x11 = COPY [[C]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
    %0:_(p0) = COPY $x10
    %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s16))
    %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
    $x10 = COPY %3(s32)
    $x11 = COPY %4(s32)
    PseudoRET implicit $x10, implicit $x11

...
---
name:            zextload_i32_i64
body:             |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: zextload_i32_i64
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: $x10 = COPY [[LOAD]](s32)
    ; CHECK-NEXT: $x11 = COPY [[C]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
    %0:_(p0) = COPY $x10
    %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s32))
    %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
    $x10 = COPY %3(s32)
    $x11 = COPY %4(s32)
    PseudoRET implicit $x10, implicit $x11

...
---
name:            sextload_i8_i16
body:             |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: sextload_i8_i16
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
    ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
    ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(p0) = COPY $x10
    %2:_(s16) = G_SEXTLOAD %0(p0) :: (load (s8))
    %3:_(s32) = G_ANYEXT %2(s16)
    $x10 = COPY %3(s32)
    PseudoRET implicit $x10

...
---
name:            sextload_i8_i32
body:             |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: sextload_i8_i32
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
    ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
    ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(p0) = COPY $x10
    %2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8))
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            sextload_i16_i32
body:             |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: sextload_i16_i32
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
    ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
    ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(p0) = COPY $x10
    %2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16))
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            sextload_i8_i64
body:             |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: sextload_i8_i64
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
    ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXTLOAD]], [[C]](s32)
    ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s32)
    ; CHECK-NEXT: $x11 = COPY [[ASHR]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
    %0:_(p0) = COPY $x10
    %2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s8))
    %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
    $x10 = COPY %3(s32)
    $x11 = COPY %4(s32)
    PseudoRET implicit $x10, implicit $x11

...
---
name:            sextload_i16_i64
body:             |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: sextload_i16_i64
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
    ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXTLOAD]], [[C]](s32)
    ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s32)
    ; CHECK-NEXT: $x11 = COPY [[ASHR]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
    %0:_(p0) = COPY $x10
    %2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s16))
    %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
    $x10 = COPY %3(s32)
    $x11 = COPY %4(s32)
    PseudoRET implicit $x10, implicit $x11

...
---
name:            sextload_i32_i64
body:             |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: sextload_i32_i64
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[C]](s32)
    ; CHECK-NEXT: $x10 = COPY [[LOAD]](s32)
    ; CHECK-NEXT: $x11 = COPY [[ASHR]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
    %0:_(p0) = COPY $x10
    %2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s32))
    %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
    $x10 = COPY %3(s32)
    $x11 = COPY %4(s32)
    PseudoRET implicit $x10, implicit $x11

...
llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-extload-rv32.mir
