llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frem-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=riscv32 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s
---
name:            frem_f32
body:             |
  bb.1.entry:
    liveins: $x10, $x11

    ; CHECK-LABEL: name: frem_f32
    ; CHECK: liveins: $x10, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
    ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
    ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
    ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32)
    ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &fmodf, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
    ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
    ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s32) = G_FREM %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            frem_f64
body:             |
  bb.1.entry:
    liveins: $x10, $x11, $x12, $x13

    ; CHECK-LABEL: name: frem_f64
    ; CHECK: liveins: $x10, $x11, $x12, $x13
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
    ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
    ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
    ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32)
    ; CHECK-NEXT: $x12 = COPY [[COPY2]](s32)
    ; CHECK-NEXT: $x13 = COPY [[COPY3]](s32)
    ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &fmod, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
    ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x10
    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x11
    ; CHECK-NEXT: $x10 = COPY [[COPY4]](s32)
    ; CHECK-NEXT: $x11 = COPY [[COPY5]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
    %2:_(s32) = COPY $x10
    %3:_(s32) = COPY $x11
    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
    %4:_(s32) = COPY $x12
    %5:_(s32) = COPY $x13
    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
    %6:_(s64) = G_FREM %0, %1
    %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
    $x10 = COPY %7(s32)
    $x11 = COPY %8(s32)
    PseudoRET implicit $x10, implicit $x11

...
---
name:            frem_f16
body:             |
  bb.0.entry:

    ; CHECK-LABEL: name: frem_f16
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
    ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
    ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
    ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
    ; CHECK-NEXT: $x10 = COPY [[FPEXT]](s32)
    ; CHECK-NEXT: $x11 = COPY [[FPEXT1]](s32)
    ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &fmodf, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
    ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
    ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY2]](s32)
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s16) = G_TRUNC %0(s32)
    %3:_(s16) = G_TRUNC %1(s32)
    %4:_(s16) = G_FREM %2, %3
    %5:_(s32) = G_ANYEXT %4(s16)
    $x10 = COPY %5(s32)
    PseudoRET implicit $x10

...
---
name:            frem_v2f32
body:             |
  bb.0.entry:

    ; CHECK-LABEL: name: frem_v2f32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $v8
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $v9
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
    ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
    ; CHECK-NEXT: $x10 = COPY [[UV]](s32)
    ; CHECK-NEXT: $x11 = COPY [[UV2]](s32)
    ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &fmodf, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
    ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
    ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
    ; CHECK-NEXT: $x10 = COPY [[UV1]](s32)
    ; CHECK-NEXT: $x11 = COPY [[UV3]](s32)
    ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &fmodf, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
    ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x10
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
    ; CHECK-NEXT: $v8 = COPY [[BUILD_VECTOR]](<2 x s32>)
    ; CHECK-NEXT: PseudoRET implicit $v8
    %0:_(<2 x s32>) = COPY $v8
    %1:_(<2 x s32>) = COPY $v9
    %2:_(<2 x s32>) = G_FREM %0, %1
    $v8 = COPY %2(<2 x s32>)
    PseudoRET implicit $v8

...