llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv64.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=regbankselect -verify-machineinstrs %s -o - \
# RUN: | FileCheck %s

---
name:            is_fpclass_f16
legalized:       true
body:             |
  bb.0:
    liveins: $f10_h

    ; CHECK-LABEL: name: is_fpclass_f16
    ; CHECK: liveins: $f10_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
    ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 152
    ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 0
    ; CHECK-NEXT: [[FCLASS:%[0-9]+]]:gprb(s64) = G_FCLASS [[COPY]](s16)
    ; CHECK-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[FCLASS]], [[C]]
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gprb(s64) = G_ICMP intpred(ne), [[AND]](s64), [[C1]]
    ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s16) = COPY $f10_h
    %3:_(s64) = G_CONSTANT i64 152
    %4:_(s64) = G_CONSTANT i64 0
    %5:_(s64) = G_FCLASS %0(s16)
    %6:_(s64) = G_AND %5, %3
    %7:_(s64) = G_ICMP intpred(ne), %6(s64), %4
    $x10 = COPY %7(s64)
    PseudoRET implicit $x10
...