llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=regbankselect \
# RUN:   -simplify-mir -verify-machineinstrs %s \
# RUN:   -o - | FileCheck %s

---
name:            sitofp_s16_s32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: sitofp_s16_s32
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
    ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:fprb(s16) = G_SITOFP [[COPY]](s32)
    ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16)
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:_(s32) = COPY $x10
    %1:_(s16) = G_SITOFP %0(s32)
    $f10_h = COPY %1(s16)
    PseudoRET implicit $f10_h

...
---
name:            uitofp_s16_s32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: uitofp_s16_s32
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
    ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:fprb(s16) = G_UITOFP [[COPY]](s32)
    ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16)
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:_(s32) = COPY $x10
    %1:_(s16) = G_UITOFP %0(s32)
    $f10_h = COPY %1(s16)
    PseudoRET implicit $f10_h

...