llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN:   -o - | FileCheck %s

---
name:            test
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test
    ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s64) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 3
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
    ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %1:_(s64) = G_READ_VLENB
    %2:_(s64) = G_CONSTANT i64 3
    %0:_(s64) = G_LSHR %1, %2(s64)
    $x10 = COPY %0(s64)
    PseudoRET implicit $x10

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