llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN:   -o - | FileCheck %s

---
name:            test_s32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_s32
    ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
    ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %1:_(s32) = G_READ_VLENB
    %2:_(s32) = G_CONSTANT i32 3
    %0:_(s32) = G_LSHR %1, %2(s32)
    $x10 = COPY %0(s32)
    PseudoRET implicit $x10

...
---
name:            test_s64
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_s64
    ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
    ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:gprb(s32) = G_MUL [[LSHR]], [[C1]]
    ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %17:_(s32) = G_READ_VLENB
    %18:_(s32) = G_CONSTANT i32 3
    %2:_(s32) = G_LSHR %17, %18(s32)
    %15:_(s32) = G_CONSTANT i32 1
    %9:_(s32) = G_MUL %2, %15
    $x10 = COPY %9(s32)
    PseudoRET implicit $x10

...