fp-arith-f16.mir | Explore in Territory

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=regbankselect \
# RUN:   -simplify-mir -verify-machineinstrs %s \
# RUN:   -o - | FileCheck %s
# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=regbankselect \
# RUN:   -simplify-mir -verify-machineinstrs %s \
# RUN:   -o - | FileCheck %s

---
name:            fadd_f16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fadd_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h
    ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s16) = G_FADD [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $f10_h = COPY [[FADD]](s16)
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:_(s16) = COPY $f10_h
    %1:_(s16) = COPY $f11_h
    %2:_(s16) = G_FADD %0, %1
    $f10_h = COPY %2(s16)
    PseudoRET implicit $f10_h

...
---
name:            fsub_f16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fsub_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h
    ; CHECK-NEXT: [[FSUB:%[0-9]+]]:fprb(s16) = G_FSUB [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $f10_h = COPY [[FSUB]](s16)
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:_(s16) = COPY $f10_h
    %1:_(s16) = COPY $f11_h
    %2:_(s16) = G_FSUB %0, %1
    $f10_h = COPY %2(s16)
    PseudoRET implicit $f10_h

...
---
name:            fmul_f16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fmul_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h
    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:fprb(s16) = G_FMUL [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $f10_h = COPY [[FMUL]](s16)
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:_(s16) = COPY $f10_h
    %1:_(s16) = COPY $f11_h
    %2:_(s16) = G_FMUL %0, %1
    $f10_h = COPY %2(s16)
    PseudoRET implicit $f10_h

...
---
name:            fdiv_f16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fdiv_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h
    ; CHECK-NEXT: [[FDIV:%[0-9]+]]:fprb(s16) = G_FDIV [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $f10_h = COPY [[FDIV]](s16)
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:_(s16) = COPY $f10_h
    %1:_(s16) = COPY $f11_h
    %2:_(s16) = G_FDIV %0, %1
    $f10_h = COPY %2(s16)
    PseudoRET implicit $f10_h

...
---
name:            fma_f16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_h, $f12_h

    ; CHECK-LABEL: name: fma_f16
    ; CHECK: liveins: $f10_h, $f11_h, $f12_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fprb(s16) = COPY $f12_h
    ; CHECK-NEXT: [[FMA:%[0-9]+]]:fprb(s16) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
    ; CHECK-NEXT: $f10_h = COPY [[FMA]](s16)
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:_(s16) = COPY $f10_h
    %1:_(s16) = COPY $f11_h
    %2:_(s16) = COPY $f12_h
    %3:_(s16) = G_FMA %0, %1, %2
    $f10_h = COPY %3(s16)
    PseudoRET implicit $f10_h

...
---
name:            fneg_f16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h

    ; CHECK-LABEL: name: fneg_f16
    ; CHECK: liveins: $f10_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:fprb(s16) = G_FNEG [[COPY]]
    ; CHECK-NEXT: $f10_h = COPY [[FNEG]](s16)
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:_(s16) = COPY $f10_h
    %1:_(s16) = G_FNEG %0
    $f10_h = COPY %1(s16)
    PseudoRET implicit $f10_h

...
---
name:            fabs_f16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h

    ; CHECK-LABEL: name: fabs_f16
    ; CHECK: liveins: $f10_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
    ; CHECK-NEXT: [[FABS:%[0-9]+]]:fprb(s16) = G_FABS [[COPY]]
    ; CHECK-NEXT: $f10_h = COPY [[FABS]](s16)
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:_(s16) = COPY $f10_h
    %1:_(s16) = G_FABS %0
    $f10_h = COPY %1(s16)
    PseudoRET implicit $f10_h

...
---
name:            fsqrt_f16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h

    ; CHECK-LABEL: name: fsqrt_f16
    ; CHECK: liveins: $f10_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
    ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:fprb(s16) = G_FSQRT [[COPY]]
    ; CHECK-NEXT: $f10_h = COPY [[FSQRT]](s16)
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:_(s16) = COPY $f10_h
    %1:_(s16) = G_FSQRT %0
    $f10_h = COPY %1(s16)
    PseudoRET implicit $f10_h

...
---
name:            fmaxnum_f16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fmaxnum_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h
    ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:fprb(s16) = G_FMAXNUM [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $f10_h = COPY [[FMAXNUM]](s16)
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:_(s16) = COPY $f10_h
    %1:_(s16) = COPY $f11_h
    %2:_(s16) = G_FMAXNUM %0, %1
    $f10_h = COPY %2(s16)
    PseudoRET implicit $f10_h

...
---
name:            fminnum_f16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fminnum_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h
    ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:fprb(s16) = G_FMINNUM [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $f10_h = COPY [[FMINNUM]](s16)
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:_(s16) = COPY $f10_h
    %1:_(s16) = COPY $f11_h
    %2:_(s16) = G_FMINNUM %0, %1
    $f10_h = COPY %2(s16)
    PseudoRET implicit $f10_h

...
---
name:            fcopysign_f16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fcopysign_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h
    ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:fprb(s16) = G_FCOPYSIGN [[COPY]], [[COPY1]](s16)
    ; CHECK-NEXT: $f10_h = COPY [[FCOPYSIGN]](s16)
    ; CHECK-NEXT: PseudoRET implicit $f10_h
    %0:_(s16) = COPY $f10_h
    %1:_(s16) = COPY $f11_h
    %2:_(s16) = G_FCOPYSIGN %0, %1
    $f10_h = COPY %2(s16)
    PseudoRET implicit $f10_h

...
llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir
