llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=regbankselect \
# RUN:   -simplify-mir -verify-machineinstrs %s \
# RUN:   -o - | FileCheck %s

---
name:            fcmp_f16
legalized:       true
body:             |
  bb.1:
    liveins: $f10_h, $f11_h

    ; CHECK-LABEL: name: fcmp_f16
    ; CHECK: liveins: $f10_h, $f11_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h
    ; CHECK-NEXT: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s16), [[COPY1]]
    ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s16) = COPY $f10_h
    %1:_(s16) = COPY $f11_h
    %4:_(s32) = G_FCMP floatpred(oeq), %0(s16), %1
    $x10 = COPY %4(s32)
    PseudoRET implicit $x10

...