llvm/llvm/test/CodeGen/RISCV/pr64935.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 < %s | FileCheck %s

define i1 @f() {
; CHECK-LABEL: f:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lui a0, 524288
; CHECK-NEXT:    not a0, a0
; CHECK-NEXT:    sltiu a0, a0, 2
; CHECK-NEXT:    xori a0, a0, 1
; CHECK-NEXT:    ret
  %B25 = shl i64 4294967296, -9223372036854775808
  %B13 = sub i64 -1, -9223372036854775808
  %C8 = icmp ugt i64 %B13, %B25
  %B5 = sub i64 0, 4294967296 ; Don't remove this instruction!
  ret i1 %C8
}