float_arithmetic_operations.mir | Explore in Territory

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |

  define void @float_add() {entry: ret void}
  define void @float_sub() {entry: ret void}
  define void @float_mul() {entry: ret void}
  define void @float_div() {entry: ret void}
  define void @double_add() {entry: ret void}
  define void @double_sub() {entry: ret void}
  define void @double_mul() {entry: ret void}
  define void @double_div() {entry: ret void}

...
---
name:            float_add
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: float_add
    ; FP32: liveins: $f12, $f14
    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP32: [[FADD_S:%[0-9]+]]:fgr32 = FADD_S [[COPY]], [[COPY1]]
    ; FP32: $f0 = COPY [[FADD_S]]
    ; FP32: RetRA implicit $f0
    ; FP64-LABEL: name: float_add
    ; FP64: liveins: $f12, $f14
    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP64: [[FADD_S:%[0-9]+]]:fgr32 = FADD_S [[COPY]], [[COPY1]]
    ; FP64: $f0 = COPY [[FADD_S]]
    ; FP64: RetRA implicit $f0
    %0:fprb(s32) = COPY $f12
    %1:fprb(s32) = COPY $f14
    %2:fprb(s32) = G_FADD %0, %1
    $f0 = COPY %2(s32)
    RetRA implicit $f0

...
---
name:            float_sub
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: float_sub
    ; FP32: liveins: $f12, $f14
    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP32: [[FSUB_S:%[0-9]+]]:fgr32 = FSUB_S [[COPY]], [[COPY1]]
    ; FP32: $f0 = COPY [[FSUB_S]]
    ; FP32: RetRA implicit $f0
    ; FP64-LABEL: name: float_sub
    ; FP64: liveins: $f12, $f14
    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP64: [[FSUB_S:%[0-9]+]]:fgr32 = FSUB_S [[COPY]], [[COPY1]]
    ; FP64: $f0 = COPY [[FSUB_S]]
    ; FP64: RetRA implicit $f0
    %0:fprb(s32) = COPY $f12
    %1:fprb(s32) = COPY $f14
    %2:fprb(s32) = G_FSUB %0, %1
    $f0 = COPY %2(s32)
    RetRA implicit $f0

...
---
name:            float_mul
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: float_mul
    ; FP32: liveins: $f12, $f14
    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP32: [[FMUL_S:%[0-9]+]]:fgr32 = FMUL_S [[COPY]], [[COPY1]]
    ; FP32: $f0 = COPY [[FMUL_S]]
    ; FP32: RetRA implicit $f0
    ; FP64-LABEL: name: float_mul
    ; FP64: liveins: $f12, $f14
    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP64: [[FMUL_S:%[0-9]+]]:fgr32 = FMUL_S [[COPY]], [[COPY1]]
    ; FP64: $f0 = COPY [[FMUL_S]]
    ; FP64: RetRA implicit $f0
    %0:fprb(s32) = COPY $f12
    %1:fprb(s32) = COPY $f14
    %2:fprb(s32) = G_FMUL %0, %1
    $f0 = COPY %2(s32)
    RetRA implicit $f0

...
---
name:            float_div
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: float_div
    ; FP32: liveins: $f12, $f14
    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP32: [[FDIV_S:%[0-9]+]]:fgr32 = FDIV_S [[COPY]], [[COPY1]]
    ; FP32: $f0 = COPY [[FDIV_S]]
    ; FP32: RetRA implicit $f0
    ; FP64-LABEL: name: float_div
    ; FP64: liveins: $f12, $f14
    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP64: [[FDIV_S:%[0-9]+]]:fgr32 = FDIV_S [[COPY]], [[COPY1]]
    ; FP64: $f0 = COPY [[FDIV_S]]
    ; FP64: RetRA implicit $f0
    %0:fprb(s32) = COPY $f12
    %1:fprb(s32) = COPY $f14
    %2:fprb(s32) = G_FDIV %0, %1
    $f0 = COPY %2(s32)
    RetRA implicit $f0

...
---
name:            double_add
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: double_add
    ; FP32: liveins: $d6, $d7
    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
    ; FP32: [[FADD_D32_:%[0-9]+]]:afgr64 = FADD_D32 [[COPY]], [[COPY1]]
    ; FP32: $d0 = COPY [[FADD_D32_]]
    ; FP32: RetRA implicit $d0
    ; FP64-LABEL: name: double_add
    ; FP64: liveins: $d6, $d7
    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
    ; FP64: [[FADD_D64_:%[0-9]+]]:fgr64 = FADD_D64 [[COPY]], [[COPY1]]
    ; FP64: $d0 = COPY [[FADD_D64_]]
    ; FP64: RetRA implicit $d0
    %0:fprb(s64) = COPY $d6
    %1:fprb(s64) = COPY $d7
    %2:fprb(s64) = G_FADD %0, %1
    $d0 = COPY %2(s64)
    RetRA implicit $d0

...
---
name:            double_sub
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: double_sub
    ; FP32: liveins: $d6, $d7
    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
    ; FP32: [[FSUB_D32_:%[0-9]+]]:afgr64 = FSUB_D32 [[COPY]], [[COPY1]]
    ; FP32: $d0 = COPY [[FSUB_D32_]]
    ; FP32: RetRA implicit $d0
    ; FP64-LABEL: name: double_sub
    ; FP64: liveins: $d6, $d7
    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
    ; FP64: [[FSUB_D64_:%[0-9]+]]:fgr64 = FSUB_D64 [[COPY]], [[COPY1]]
    ; FP64: $d0 = COPY [[FSUB_D64_]]
    ; FP64: RetRA implicit $d0
    %0:fprb(s64) = COPY $d6
    %1:fprb(s64) = COPY $d7
    %2:fprb(s64) = G_FSUB %0, %1
    $d0 = COPY %2(s64)
    RetRA implicit $d0

...
---
name:            double_mul
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: double_mul
    ; FP32: liveins: $d6, $d7
    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
    ; FP32: [[FMUL_D32_:%[0-9]+]]:afgr64 = FMUL_D32 [[COPY]], [[COPY1]]
    ; FP32: $d0 = COPY [[FMUL_D32_]]
    ; FP32: RetRA implicit $d0
    ; FP64-LABEL: name: double_mul
    ; FP64: liveins: $d6, $d7
    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
    ; FP64: [[FMUL_D64_:%[0-9]+]]:fgr64 = FMUL_D64 [[COPY]], [[COPY1]]
    ; FP64: $d0 = COPY [[FMUL_D64_]]
    ; FP64: RetRA implicit $d0
    %0:fprb(s64) = COPY $d6
    %1:fprb(s64) = COPY $d7
    %2:fprb(s64) = G_FMUL %0, %1
    $d0 = COPY %2(s64)
    RetRA implicit $d0

...
---
name:            double_div
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: double_div
    ; FP32: liveins: $d6, $d7
    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
    ; FP32: [[FDIV_D32_:%[0-9]+]]:afgr64 = FDIV_D32 [[COPY]], [[COPY1]]
    ; FP32: $d0 = COPY [[FDIV_D32_]]
    ; FP32: RetRA implicit $d0
    ; FP64-LABEL: name: double_div
    ; FP64: liveins: $d6, $d7
    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
    ; FP64: [[FDIV_D64_:%[0-9]+]]:fgr64 = FDIV_D64 [[COPY]], [[COPY1]]
    ; FP64: $d0 = COPY [[FDIV_D64_]]
    ; FP64: RetRA implicit $d0
    %0:fprb(s64) = COPY $d6
    %1:fprb(s64) = COPY $d7
    %2:fprb(s64) = G_FDIV %0, %1
    $d0 = COPY %2(s64)
    RetRA implicit $d0

...
llvm/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/float_arithmetic_operations.mir
