llvm/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub_vec.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

  define void @sub_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
  define void @sub_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }
  define void @sub_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }
  define void @sub_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }

...
---
name:            sub_v16i8
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1, $a2

    ; P5600-LABEL: name: sub_v16i8
    ; P5600: liveins: $a0, $a1, $a2
    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
    ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load (<16 x s8>) from %ir.a)
    ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load (<16 x s8>) from %ir.b)
    ; P5600: [[SUBV_B:%[0-9]+]]:msa128b = SUBV_B [[LD_B1]], [[LD_B]]
    ; P5600: ST_B [[SUBV_B]], [[COPY2]], 0 :: (store (<16 x s8>) into %ir.c)
    ; P5600: RetRA
    %0:gprb(p0) = COPY $a0
    %1:gprb(p0) = COPY $a1
    %2:gprb(p0) = COPY $a2
    %3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
    %4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
    %5:fprb(<16 x s8>) = G_SUB %4, %3
    G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)
    RetRA

...
---
name:            sub_v8i16
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1, $a2

    ; P5600-LABEL: name: sub_v8i16
    ; P5600: liveins: $a0, $a1, $a2
    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
    ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load (<8 x s16>) from %ir.a)
    ; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load (<8 x s16>) from %ir.b)
    ; P5600: [[SUBV_H:%[0-9]+]]:msa128h = SUBV_H [[LD_H1]], [[LD_H]]
    ; P5600: ST_H [[SUBV_H]], [[COPY2]], 0 :: (store (<8 x s16>) into %ir.c)
    ; P5600: RetRA
    %0:gprb(p0) = COPY $a0
    %1:gprb(p0) = COPY $a1
    %2:gprb(p0) = COPY $a2
    %3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
    %4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
    %5:fprb(<8 x s16>) = G_SUB %4, %3
    G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)
    RetRA

...
---
name:            sub_v4i32
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1, $a2

    ; P5600-LABEL: name: sub_v4i32
    ; P5600: liveins: $a0, $a1, $a2
    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
    ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
    ; P5600: [[SUBV_W:%[0-9]+]]:msa128w = SUBV_W [[LD_W1]], [[LD_W]]
    ; P5600: ST_W [[SUBV_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
    ; P5600: RetRA
    %0:gprb(p0) = COPY $a0
    %1:gprb(p0) = COPY $a1
    %2:gprb(p0) = COPY $a2
    %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
    %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
    %5:fprb(<4 x s32>) = G_SUB %4, %3
    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
    RetRA

...
---
name:            sub_v2i64
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1, $a2

    ; P5600-LABEL: name: sub_v2i64
    ; P5600: liveins: $a0, $a1, $a2
    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
    ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
    ; P5600: [[SUBV_D:%[0-9]+]]:msa128d = SUBV_D [[LD_D1]], [[LD_D]]
    ; P5600: ST_D [[SUBV_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
    ; P5600: RetRA
    %0:gprb(p0) = COPY $a0
    %1:gprb(p0) = COPY $a1
    %2:gprb(p0) = COPY $a2
    %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
    %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
    %5:fprb(<2 x s64>) = G_SUB %4, %3
    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
    RetRA

...