llvm/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fsqrt.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |

  define void @sqrt_f32() {entry: ret void}
  define void @sqrt_f64() {entry: ret void}

...
---
name:            sqrt_f32
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12

    ; FP32-LABEL: name: sqrt_f32
    ; FP32: liveins: $f12
    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP32: [[FSQRT_S:%[0-9]+]]:fgr32 = FSQRT_S [[COPY]]
    ; FP32: $f0 = COPY [[FSQRT_S]]
    ; FP32: RetRA implicit $f0
    ; FP64-LABEL: name: sqrt_f32
    ; FP64: liveins: $f12
    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP64: [[FSQRT_S:%[0-9]+]]:fgr32 = FSQRT_S [[COPY]]
    ; FP64: $f0 = COPY [[FSQRT_S]]
    ; FP64: RetRA implicit $f0
    %0:fprb(s32) = COPY $f12
    %1:fprb(s32) = G_FSQRT %0
    $f0 = COPY %1(s32)
    RetRA implicit $f0

...
---
name:            sqrt_f64
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6

    ; FP32-LABEL: name: sqrt_f64
    ; FP32: liveins: $d6
    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; FP32: [[FSQRT_D32_:%[0-9]+]]:afgr64 = FSQRT_D32 [[COPY]]
    ; FP32: $d0 = COPY [[FSQRT_D32_]]
    ; FP32: RetRA implicit $d0
    ; FP64-LABEL: name: sqrt_f64
    ; FP64: liveins: $d6
    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
    ; FP64: [[FSQRT_D64_:%[0-9]+]]:fgr64 = FSQRT_D64 [[COPY]]
    ; FP64: $d0 = COPY [[FSQRT_D64_]]
    ; FP64: RetRA implicit $d0
    %0:fprb(s64) = COPY $d6
    %1:fprb(s64) = G_FSQRT %0
    $d0 = COPY %1(s64)
    RetRA implicit $d0

...