load_store_vec.mir | Explore in Territory

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=msa,+fp64 -mattr=nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

  define void @load_store_v16i8(ptr %a, ptr %b) { entry: ret void }
  define void @load_store_v8i16(ptr %a, ptr %b) { entry: ret void }
  define void @load_store_v4i32(ptr %a, ptr %b) { entry: ret void }
  define void @load_store_v2i64(ptr %a, ptr %b) { entry: ret void }
  define void @load_store_v4f32(ptr %a, ptr %b) { entry: ret void }
  define void @load_store_v2f64(ptr %a, ptr %b) { entry: ret void }

...
---
name:            load_store_v16i8
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; P5600-LABEL: name: load_store_v16i8
    ; P5600: liveins: $a0, $a1
    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
    ; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
    ; P5600: G_STORE [[LOAD]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>) into %ir.a)
    ; P5600: RetRA
    %0:_(p0) = COPY $a0
    %1:_(p0) = COPY $a1
    %2:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
    G_STORE %2(<16 x s8>), %0(p0) :: (store (<16 x s8>) into %ir.a)
    RetRA

...
---
name:            load_store_v8i16
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; P5600-LABEL: name: load_store_v8i16
    ; P5600: liveins: $a0, $a1
    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
    ; P5600: [[LOAD:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
    ; P5600: G_STORE [[LOAD]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>) into %ir.a)
    ; P5600: RetRA
    %0:_(p0) = COPY $a0
    %1:_(p0) = COPY $a1
    %2:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
    G_STORE %2(<8 x s16>), %0(p0) :: (store (<8 x s16>) into %ir.a)
    RetRA

...
---
name:            load_store_v4i32
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; P5600-LABEL: name: load_store_v4i32
    ; P5600: liveins: $a0, $a1
    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
    ; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
    ; P5600: G_STORE [[LOAD]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>) into %ir.a)
    ; P5600: RetRA
    %0:_(p0) = COPY $a0
    %1:_(p0) = COPY $a1
    %2:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
    G_STORE %2(<4 x s32>), %0(p0) :: (store (<4 x s32>) into %ir.a)
    RetRA

...
---
name:            load_store_v2i64
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; P5600-LABEL: name: load_store_v2i64
    ; P5600: liveins: $a0, $a1
    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
    ; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
    ; P5600: G_STORE [[LOAD]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>) into %ir.a)
    ; P5600: RetRA
    %0:_(p0) = COPY $a0
    %1:_(p0) = COPY $a1
    %2:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
    G_STORE %2(<2 x s64>), %0(p0) :: (store (<2 x s64>) into %ir.a)
    RetRA

...
---
name:            load_store_v4f32
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; P5600-LABEL: name: load_store_v4f32
    ; P5600: liveins: $a0, $a1
    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
    ; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
    ; P5600: G_STORE [[LOAD]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>) into %ir.a)
    ; P5600: RetRA
    %0:_(p0) = COPY $a0
    %1:_(p0) = COPY $a1
    %2:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
    G_STORE %2(<4 x s32>), %0(p0) :: (store (<4 x s32>) into %ir.a)
    RetRA

...
---
name:            load_store_v2f64
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; P5600-LABEL: name: load_store_v2f64
    ; P5600: liveins: $a0, $a1
    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
    ; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
    ; P5600: G_STORE [[LOAD]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>) into %ir.a)
    ; P5600: RetRA
    %0:_(p0) = COPY $a0
    %1:_(p0) = COPY $a1
    %2:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
    G_STORE %2(<2 x s64>), %0(p0) :: (store (<2 x s64>) into %ir.a)
    RetRA

...
llvm/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir
