# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @outgoing_gpr(ptr %i32_ptr) {entry: ret void}
define void @outgoing_fpr(ptr %float_ptr) {entry: ret void}
define void @outgoing_gpr_instr(ptr %i32_ptr1, ptr %i32_ptr2) {entry: ret void}
define void @outgoing_fpr_instr(ptr %float_ptr1, ptr %float_ptr2) {entry: ret void}
define void @incoming_gpr(ptr %a) {entry: ret void}
define void @incoming_fpr(ptr %a) {entry: ret void}
define void @incoming_i32_instr(ptr %i32_ptr) {entry: ret void}
define void @incoming_float_instr(ptr %float_ptr) {entry: ret void}
...
---
name: outgoing_gpr
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: outgoing_gpr
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.i32_ptr)
; MIPS32: $v0 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0
%1:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.i32_ptr)
$v0 = COPY %1(s32)
RetRA implicit $v0
...
---
name: outgoing_fpr
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: outgoing_fpr
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.float_ptr)
; MIPS32: $f0 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $f0
%0:_(p0) = COPY $a0
%1:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.float_ptr)
$f0 = COPY %1(s32)
RetRA implicit $f0
...
---
name: outgoing_gpr_instr
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: outgoing_gpr_instr
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.i32_ptr1)
; MIPS32: [[LOAD1:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY1]](p0) :: (load (s32) from %ir.i32_ptr2)
; MIPS32: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[LOAD1]], [[LOAD]]
; MIPS32: $v0 = COPY [[ADD]](s32)
; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.i32_ptr1)
%3:_(s32) = G_LOAD %1(p0) :: (load (s32) from %ir.i32_ptr2)
%4:_(s32) = G_ADD %3, %2
$v0 = COPY %4(s32)
RetRA implicit $v0
...
---
name: outgoing_fpr_instr
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: outgoing_fpr_instr
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
; MIPS32: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.float_ptr1)
; MIPS32: [[LOAD1:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY1]](p0) :: (load (s32) from %ir.float_ptr2)
; MIPS32: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[LOAD]], [[LOAD1]]
; MIPS32: $f0 = COPY [[FADD]](s32)
; MIPS32: RetRA implicit $f0
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.float_ptr1)
%3:_(s32) = G_LOAD %1(p0) :: (load (s32) from %ir.float_ptr2)
%4:_(s32) = G_FADD %2, %3
$f0 = COPY %4(s32)
RetRA implicit $f0
...
---
name: incoming_gpr
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; MIPS32-LABEL: name: incoming_gpr
; MIPS32: liveins: $a0, $a1, $a2
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.a)
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY1]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[LOAD]], [[COPY]]
; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%2:_(p0) = COPY $a2
%4:_(s32) = G_LOAD %2(p0) :: (load (s32) from %ir.a)
%7:_(s32) = G_CONSTANT i32 1
%8:_(s32) = COPY %3(s32)
%6:_(s32) = G_AND %8, %7
%5:_(s32) = G_SELECT %6(s32), %4, %0
$v0 = COPY %5(s32)
RetRA implicit $v0
...
---
name: incoming_fpr
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a1, $a2, $f12
; MIPS32-LABEL: name: incoming_fpr
; MIPS32: liveins: $a1, $a2, $f12
; MIPS32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
; MIPS32: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.a)
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY1]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s32), [[LOAD]], [[COPY]]
; MIPS32: $f0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $f0
%0:_(s32) = COPY $f12
%3:_(s32) = COPY $a1
%2:_(p0) = COPY $a2
%4:_(s32) = G_LOAD %2(p0) :: (load (s32) from %ir.a)
%7:_(s32) = G_CONSTANT i32 1
%8:_(s32) = COPY %3(s32)
%6:_(s32) = G_AND %8, %7
%5:_(s32) = G_SELECT %6(s32), %4, %0
$f0 = COPY %5(s32)
RetRA implicit $f0
...
---
name: incoming_i32_instr
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2, $a3
; MIPS32-LABEL: name: incoming_i32_instr
; MIPS32: liveins: $a0, $a1, $a2, $a3
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY $a3
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.i32_ptr)
; MIPS32: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[COPY1]], [[COPY]]
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY4:%[0-9]+]]:gprb(s32) = COPY [[COPY3]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY4]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[LOAD]], [[ADD]]
; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(p0) = COPY $a2
%4:_(s32) = COPY $a3
%5:_(s32) = G_LOAD %2(p0) :: (load (s32) from %ir.i32_ptr)
%6:_(s32) = G_ADD %1, %0
%9:_(s32) = G_CONSTANT i32 1
%10:_(s32) = COPY %4(s32)
%8:_(s32) = G_AND %10, %9
%7:_(s32) = G_SELECT %8(s32), %5, %6
$v0 = COPY %7(s32)
RetRA implicit $v0
...
---
name: incoming_float_instr
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a2, $a3, $f12, $f14
; MIPS32-LABEL: name: incoming_float_instr
; MIPS32: liveins: $a2, $a3, $f12, $f14
; MIPS32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
; MIPS32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY $a3
; MIPS32: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.float_ptr)
; MIPS32: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY1]], [[COPY]]
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY4:%[0-9]+]]:gprb(s32) = COPY [[COPY3]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY4]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s32), [[LOAD]], [[FADD]]
; MIPS32: $f0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $f0
%0:_(s32) = COPY $f12
%1:_(s32) = COPY $f14
%2:_(p0) = COPY $a2
%4:_(s32) = COPY $a3
%5:_(s32) = G_LOAD %2(p0) :: (load (s32) from %ir.float_ptr)
%6:_(s32) = G_FADD %1, %0
%9:_(s32) = G_CONSTANT i32 1
%10:_(s32) = COPY %4(s32)
%8:_(s32) = G_AND %10, %9
%7:_(s32) = G_SELECT %8(s32), %5, %6
$f0 = COPY %7(s32)
RetRA implicit $f0
...
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