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llvm/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir 

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |

  define void @oeq_s() {entry: ret void}
  define void @oeq_d() {entry: ret void}

...
---
name:            oeq_s
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: oeq_s
    ; FP32: liveins: $f12, $f14
    ; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
    ; FP32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
    ; FP32: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
    ; FP32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32)
    ; FP32: $v0 = COPY [[COPY2]](s32)
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: oeq_s
    ; FP64: liveins: $f12, $f14
    ; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
    ; FP64: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
    ; FP64: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
    ; FP64: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32)
    ; FP64: $v0 = COPY [[COPY2]](s32)
    ; FP64: RetRA implicit $v0
    %0:_(s32) = COPY $f12
    %1:_(s32) = COPY $f14
    %4:_(s32) = G_FCMP floatpred(oeq), %0(s32), %1
    %3:_(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            oeq_d
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: oeq_d
    ; FP32: liveins: $d6, $d7
    ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
    ; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
    ; FP32: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]]
    ; FP32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32)
    ; FP32: $v0 = COPY [[COPY2]](s32)
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: oeq_d
    ; FP64: liveins: $d6, $d7
    ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
    ; FP64: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
    ; FP64: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]]
    ; FP64: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32)
    ; FP64: $v0 = COPY [[COPY2]](s32)
    ; FP64: RetRA implicit $v0
    %0:_(s64) = COPY $d6
    %1:_(s64) = COPY $d7
    %4:_(s32) = G_FCMP floatpred(oeq), %0(s64), %1
    %3:_(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...