; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=MIPS
; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=MIPS32
; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=32R2
; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=32R2
; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=32R2
; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=32R6
; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=MIPS3
; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=MIPS64
; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=MIPS64
; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=MIPS64R2
; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=MIPS64R2
; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=MIPS64R2
; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=MIPS64R6
; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=MMR3
; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=MMR6
define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) {
; MIPS-LABEL: ashr_i1:
; MIPS: # %bb.0: # %entry
; MIPS-NEXT: jr $ra
; MIPS-NEXT: move $2, $4
;
; MIPS32-LABEL: ashr_i1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: move $2, $4
;
; 32R2-LABEL: ashr_i1:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: jr $ra
; 32R2-NEXT: move $2, $4
;
; 32R6-LABEL: ashr_i1:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: jr $ra
; 32R6-NEXT: move $2, $4
;
; MIPS3-LABEL: ashr_i1:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: move $2, $4
;
; MIPS64-LABEL: ashr_i1:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: move $2, $4
;
; MIPS64R2-LABEL: ashr_i1:
; MIPS64R2: # %bb.0: # %entry
; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: move $2, $4
;
; MIPS64R6-LABEL: ashr_i1:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: jr $ra
; MIPS64R6-NEXT: move $2, $4
;
; MMR3-LABEL: ashr_i1:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: move $2, $4
; MMR3-NEXT: jrc $ra
;
; MMR6-LABEL: ashr_i1:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: move $2, $4
; MMR6-NEXT: jrc $ra
entry:
%r = ashr i1 %a, %b
ret i1 %r
}
; FIXME: The andi instruction is redundant.
define signext i8 @ashr_i8(i8 signext %a, i8 signext %b) {
; MIPS-LABEL: ashr_i8:
; MIPS: # %bb.0: # %entry
; MIPS-NEXT: jr $ra
; MIPS-NEXT: srav $2, $4, $5
;
; MIPS32-LABEL: ashr_i8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: srav $2, $4, $5
;
; 32R2-LABEL: ashr_i8:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: jr $ra
; 32R2-NEXT: srav $2, $4, $5
;
; 32R6-LABEL: ashr_i8:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: jr $ra
; 32R6-NEXT: srav $2, $4, $5
;
; MIPS3-LABEL: ashr_i8:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: srav $2, $4, $5
;
; MIPS64-LABEL: ashr_i8:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: srav $2, $4, $5
;
; MIPS64R2-LABEL: ashr_i8:
; MIPS64R2: # %bb.0: # %entry
; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: srav $2, $4, $5
;
; MIPS64R6-LABEL: ashr_i8:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: jr $ra
; MIPS64R6-NEXT: srav $2, $4, $5
;
; MMR3-LABEL: ashr_i8:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: andi16 $2, $5, 255
; MMR3-NEXT: jr $ra
; MMR3-NEXT: srav $2, $4, $2
;
; MMR6-LABEL: ashr_i8:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: andi16 $2, $5, 255
; MMR6-NEXT: srav $2, $4, $2
; MMR6-NEXT: jrc $ra
entry:
%r = ashr i8 %a, %b
ret i8 %r
}
; FIXME: The andi instruction is redundant.
define signext i16 @ashr_i16(i16 signext %a, i16 signext %b) {
; MIPS-LABEL: ashr_i16:
; MIPS: # %bb.0: # %entry
; MIPS-NEXT: jr $ra
; MIPS-NEXT: srav $2, $4, $5
;
; MIPS32-LABEL: ashr_i16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: srav $2, $4, $5
;
; 32R2-LABEL: ashr_i16:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: jr $ra
; 32R2-NEXT: srav $2, $4, $5
;
; 32R6-LABEL: ashr_i16:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: jr $ra
; 32R6-NEXT: srav $2, $4, $5
;
; MIPS3-LABEL: ashr_i16:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: srav $2, $4, $5
;
; MIPS64-LABEL: ashr_i16:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: srav $2, $4, $5
;
; MIPS64R2-LABEL: ashr_i16:
; MIPS64R2: # %bb.0: # %entry
; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: srav $2, $4, $5
;
; MIPS64R6-LABEL: ashr_i16:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: jr $ra
; MIPS64R6-NEXT: srav $2, $4, $5
;
; MMR3-LABEL: ashr_i16:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: andi16 $2, $5, 65535
; MMR3-NEXT: jr $ra
; MMR3-NEXT: srav $2, $4, $2
;
; MMR6-LABEL: ashr_i16:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: andi16 $2, $5, 65535
; MMR6-NEXT: srav $2, $4, $2
; MMR6-NEXT: jrc $ra
entry:
%r = ashr i16 %a, %b
ret i16 %r
}
define signext i32 @ashr_i32(i32 signext %a, i32 signext %b) {
; MIPS-LABEL: ashr_i32:
; MIPS: # %bb.0: # %entry
; MIPS-NEXT: jr $ra
; MIPS-NEXT: srav $2, $4, $5
;
; MIPS32-LABEL: ashr_i32:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: srav $2, $4, $5
;
; 32R2-LABEL: ashr_i32:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: jr $ra
; 32R2-NEXT: srav $2, $4, $5
;
; 32R6-LABEL: ashr_i32:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: jr $ra
; 32R6-NEXT: srav $2, $4, $5
;
; MIPS3-LABEL: ashr_i32:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: srav $2, $4, $5
;
; MIPS64-LABEL: ashr_i32:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: srav $2, $4, $5
;
; MIPS64R2-LABEL: ashr_i32:
; MIPS64R2: # %bb.0: # %entry
; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: srav $2, $4, $5
;
; MIPS64R6-LABEL: ashr_i32:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: jr $ra
; MIPS64R6-NEXT: srav $2, $4, $5
;
; MMR3-LABEL: ashr_i32:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: jr $ra
; MMR3-NEXT: srav $2, $4, $5
;
; MMR6-LABEL: ashr_i32:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: srav $2, $4, $5
; MMR6-NEXT: jrc $ra
entry:
%r = ashr i32 %a, %b
ret i32 %r
}
define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) {
; MIPS-LABEL: ashr_i64:
; MIPS: # %bb.0: # %entry
; MIPS-NEXT: andi $1, $7, 32
; MIPS-NEXT: bnez $1, $BB4_2
; MIPS-NEXT: srav $3, $4, $7
; MIPS-NEXT: # %bb.1: # %entry
; MIPS-NEXT: srlv $1, $5, $7
; MIPS-NEXT: xori $2, $7, 31
; MIPS-NEXT: sll $4, $4, 1
; MIPS-NEXT: sllv $2, $4, $2
; MIPS-NEXT: or $1, $2, $1
; MIPS-NEXT: move $2, $3
; MIPS-NEXT: jr $ra
; MIPS-NEXT: move $3, $1
; MIPS-NEXT: $BB4_2:
; MIPS-NEXT: jr $ra
; MIPS-NEXT: sra $2, $4, 31
;
; MIPS32-LABEL: ashr_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: srlv $1, $5, $7
; MIPS32-NEXT: xori $2, $7, 31
; MIPS32-NEXT: sll $3, $4, 1
; MIPS32-NEXT: sllv $2, $3, $2
; MIPS32-NEXT: or $3, $2, $1
; MIPS32-NEXT: srav $2, $4, $7
; MIPS32-NEXT: andi $1, $7, 32
; MIPS32-NEXT: movn $3, $2, $1
; MIPS32-NEXT: sra $4, $4, 31
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: movn $2, $4, $1
;
; 32R2-LABEL: ashr_i64:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: srlv $1, $5, $7
; 32R2-NEXT: xori $2, $7, 31
; 32R2-NEXT: sll $3, $4, 1
; 32R2-NEXT: sllv $2, $3, $2
; 32R2-NEXT: or $3, $2, $1
; 32R2-NEXT: srav $2, $4, $7
; 32R2-NEXT: andi $1, $7, 32
; 32R2-NEXT: movn $3, $2, $1
; 32R2-NEXT: sra $4, $4, 31
; 32R2-NEXT: jr $ra
; 32R2-NEXT: movn $2, $4, $1
;
; 32R6-LABEL: ashr_i64:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: srav $1, $4, $7
; 32R6-NEXT: andi $3, $7, 32
; 32R6-NEXT: seleqz $2, $1, $3
; 32R6-NEXT: sra $6, $4, 31
; 32R6-NEXT: selnez $6, $6, $3
; 32R6-NEXT: or $2, $6, $2
; 32R6-NEXT: srlv $5, $5, $7
; 32R6-NEXT: xori $6, $7, 31
; 32R6-NEXT: sll $4, $4, 1
; 32R6-NEXT: sllv $4, $4, $6
; 32R6-NEXT: or $4, $4, $5
; 32R6-NEXT: seleqz $4, $4, $3
; 32R6-NEXT: selnez $1, $1, $3
; 32R6-NEXT: jr $ra
; 32R6-NEXT: or $3, $1, $4
;
; MIPS3-LABEL: ashr_i64:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: dsrav $2, $4, $5
;
; MIPS64-LABEL: ashr_i64:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: dsrav $2, $4, $5
;
; MIPS64R2-LABEL: ashr_i64:
; MIPS64R2: # %bb.0: # %entry
; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: dsrav $2, $4, $5
;
; MIPS64R6-LABEL: ashr_i64:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: jr $ra
; MIPS64R6-NEXT: dsrav $2, $4, $5
;
; MMR3-LABEL: ashr_i64:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: srlv $2, $5, $7
; MMR3-NEXT: xori $1, $7, 31
; MMR3-NEXT: sll16 $3, $4, 1
; MMR3-NEXT: sllv $3, $3, $1
; MMR3-NEXT: or16 $3, $2
; MMR3-NEXT: srav $2, $4, $7
; MMR3-NEXT: andi16 $5, $7, 32
; MMR3-NEXT: movn $3, $2, $5
; MMR3-NEXT: sra $1, $4, 31
; MMR3-NEXT: jr $ra
; MMR3-NEXT: movn $2, $1, $5
;
; MMR6-LABEL: ashr_i64:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: srav $1, $4, $7
; MMR6-NEXT: andi16 $3, $7, 32
; MMR6-NEXT: seleqz $2, $1, $3
; MMR6-NEXT: sra $6, $4, 31
; MMR6-NEXT: selnez $6, $6, $3
; MMR6-NEXT: or $2, $6, $2
; MMR6-NEXT: srlv $5, $5, $7
; MMR6-NEXT: xori $6, $7, 31
; MMR6-NEXT: sll16 $4, $4, 1
; MMR6-NEXT: sllv $4, $4, $6
; MMR6-NEXT: or $4, $4, $5
; MMR6-NEXT: seleqz $4, $4, $3
; MMR6-NEXT: selnez $1, $1, $3
; MMR6-NEXT: or $3, $1, $4
; MMR6-NEXT: jrc $ra
entry:
%r = ashr i64 %a, %b
ret i64 %r
}
define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
; MIPS-LABEL: ashr_i128:
; MIPS: # %bb.0: # %entry
; MIPS-NEXT: addiu $sp, $sp, -32
; MIPS-NEXT: .cfi_def_cfa_offset 32
; MIPS-NEXT: sra $1, $4, 31
; MIPS-NEXT: sw $7, 28($sp)
; MIPS-NEXT: sw $6, 24($sp)
; MIPS-NEXT: sw $5, 20($sp)
; MIPS-NEXT: sw $4, 16($sp)
; MIPS-NEXT: sw $1, 12($sp)
; MIPS-NEXT: sw $1, 8($sp)
; MIPS-NEXT: sw $1, 4($sp)
; MIPS-NEXT: sw $1, 0($sp)
; MIPS-NEXT: addiu $1, $sp, 0
; MIPS-NEXT: addiu $1, $1, 16
; MIPS-NEXT: lw $2, 60($sp)
; MIPS-NEXT: srl $3, $2, 3
; MIPS-NEXT: andi $3, $3, 12
; MIPS-NEXT: subu $1, $1, $3
; MIPS-NEXT: lw $3, 4($1)
; MIPS-NEXT: lw $5, 8($1)
; MIPS-NEXT: srlv $4, $5, $2
; MIPS-NEXT: sll $6, $3, 1
; MIPS-NEXT: andi $7, $2, 31
; MIPS-NEXT: xori $7, $7, 31
; MIPS-NEXT: sllv $6, $6, $7
; MIPS-NEXT: srlv $3, $3, $2
; MIPS-NEXT: lw $8, 0($1)
; MIPS-NEXT: sll $9, $8, 1
; MIPS-NEXT: sllv $9, $9, $7
; MIPS-NEXT: or $3, $3, $9
; MIPS-NEXT: or $4, $4, $6
; MIPS-NEXT: lw $1, 12($1)
; MIPS-NEXT: srlv $1, $1, $2
; MIPS-NEXT: sll $5, $5, 1
; MIPS-NEXT: sllv $5, $5, $7
; MIPS-NEXT: or $5, $1, $5
; MIPS-NEXT: srav $2, $8, $2
; MIPS-NEXT: jr $ra
; MIPS-NEXT: addiu $sp, $sp, 32
;
; MIPS32-LABEL: ashr_i128:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -32
; MIPS32-NEXT: .cfi_def_cfa_offset 32
; MIPS32-NEXT: sra $1, $4, 31
; MIPS32-NEXT: sw $7, 28($sp)
; MIPS32-NEXT: sw $6, 24($sp)
; MIPS32-NEXT: sw $5, 20($sp)
; MIPS32-NEXT: sw $4, 16($sp)
; MIPS32-NEXT: sw $1, 12($sp)
; MIPS32-NEXT: sw $1, 8($sp)
; MIPS32-NEXT: sw $1, 4($sp)
; MIPS32-NEXT: sw $1, 0($sp)
; MIPS32-NEXT: addiu $1, $sp, 0
; MIPS32-NEXT: addiu $1, $1, 16
; MIPS32-NEXT: lw $2, 60($sp)
; MIPS32-NEXT: srl $3, $2, 3
; MIPS32-NEXT: andi $3, $3, 12
; MIPS32-NEXT: subu $1, $1, $3
; MIPS32-NEXT: lw $3, 4($1)
; MIPS32-NEXT: lw $5, 8($1)
; MIPS32-NEXT: srlv $4, $5, $2
; MIPS32-NEXT: sll $6, $3, 1
; MIPS32-NEXT: andi $7, $2, 31
; MIPS32-NEXT: xori $7, $7, 31
; MIPS32-NEXT: sllv $6, $6, $7
; MIPS32-NEXT: srlv $3, $3, $2
; MIPS32-NEXT: lw $8, 0($1)
; MIPS32-NEXT: sll $9, $8, 1
; MIPS32-NEXT: sllv $9, $9, $7
; MIPS32-NEXT: or $3, $3, $9
; MIPS32-NEXT: or $4, $4, $6
; MIPS32-NEXT: lw $1, 12($1)
; MIPS32-NEXT: srlv $1, $1, $2
; MIPS32-NEXT: sll $5, $5, 1
; MIPS32-NEXT: sllv $5, $5, $7
; MIPS32-NEXT: or $5, $1, $5
; MIPS32-NEXT: srav $2, $8, $2
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: addiu $sp, $sp, 32
;
; 32R2-LABEL: ashr_i128:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: addiu $sp, $sp, -32
; 32R2-NEXT: .cfi_def_cfa_offset 32
; 32R2-NEXT: sra $1, $4, 31
; 32R2-NEXT: sw $7, 28($sp)
; 32R2-NEXT: sw $6, 24($sp)
; 32R2-NEXT: sw $5, 20($sp)
; 32R2-NEXT: sw $4, 16($sp)
; 32R2-NEXT: sw $1, 12($sp)
; 32R2-NEXT: sw $1, 8($sp)
; 32R2-NEXT: sw $1, 4($sp)
; 32R2-NEXT: sw $1, 0($sp)
; 32R2-NEXT: addiu $1, $sp, 0
; 32R2-NEXT: addiu $1, $1, 16
; 32R2-NEXT: lw $2, 60($sp)
; 32R2-NEXT: srl $3, $2, 3
; 32R2-NEXT: andi $3, $3, 12
; 32R2-NEXT: subu $1, $1, $3
; 32R2-NEXT: lw $3, 4($1)
; 32R2-NEXT: lw $5, 8($1)
; 32R2-NEXT: srlv $4, $5, $2
; 32R2-NEXT: sll $6, $3, 1
; 32R2-NEXT: andi $7, $2, 31
; 32R2-NEXT: xori $7, $7, 31
; 32R2-NEXT: sllv $6, $6, $7
; 32R2-NEXT: srlv $3, $3, $2
; 32R2-NEXT: lw $8, 0($1)
; 32R2-NEXT: sll $9, $8, 1
; 32R2-NEXT: sllv $9, $9, $7
; 32R2-NEXT: or $3, $3, $9
; 32R2-NEXT: or $4, $4, $6
; 32R2-NEXT: lw $1, 12($1)
; 32R2-NEXT: srlv $1, $1, $2
; 32R2-NEXT: sll $5, $5, 1
; 32R2-NEXT: sllv $5, $5, $7
; 32R2-NEXT: or $5, $1, $5
; 32R2-NEXT: srav $2, $8, $2
; 32R2-NEXT: jr $ra
; 32R2-NEXT: addiu $sp, $sp, 32
;
; 32R6-LABEL: ashr_i128:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: addiu $sp, $sp, -32
; 32R6-NEXT: .cfi_def_cfa_offset 32
; 32R6-NEXT: sra $1, $4, 31
; 32R6-NEXT: sw $7, 28($sp)
; 32R6-NEXT: sw $6, 24($sp)
; 32R6-NEXT: sw $5, 20($sp)
; 32R6-NEXT: sw $4, 16($sp)
; 32R6-NEXT: sw $1, 12($sp)
; 32R6-NEXT: sw $1, 8($sp)
; 32R6-NEXT: sw $1, 4($sp)
; 32R6-NEXT: sw $1, 0($sp)
; 32R6-NEXT: addiu $1, $sp, 0
; 32R6-NEXT: addiu $1, $1, 16
; 32R6-NEXT: lw $2, 60($sp)
; 32R6-NEXT: srl $3, $2, 3
; 32R6-NEXT: andi $3, $3, 12
; 32R6-NEXT: subu $1, $1, $3
; 32R6-NEXT: lw $3, 4($1)
; 32R6-NEXT: lw $5, 8($1)
; 32R6-NEXT: srlv $4, $5, $2
; 32R6-NEXT: sll $6, $3, 1
; 32R6-NEXT: andi $7, $2, 31
; 32R6-NEXT: xori $7, $7, 31
; 32R6-NEXT: sllv $6, $6, $7
; 32R6-NEXT: srlv $3, $3, $2
; 32R6-NEXT: lw $8, 0($1)
; 32R6-NEXT: sll $9, $8, 1
; 32R6-NEXT: sllv $9, $9, $7
; 32R6-NEXT: or $3, $3, $9
; 32R6-NEXT: or $4, $4, $6
; 32R6-NEXT: lw $1, 12($1)
; 32R6-NEXT: srlv $1, $1, $2
; 32R6-NEXT: sll $5, $5, 1
; 32R6-NEXT: sllv $5, $5, $7
; 32R6-NEXT: or $5, $1, $5
; 32R6-NEXT: srav $2, $8, $2
; 32R6-NEXT: jr $ra
; 32R6-NEXT: addiu $sp, $sp, 32
;
; MIPS3-LABEL: ashr_i128:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: sll $2, $7, 0
; MIPS3-NEXT: andi $1, $2, 64
; MIPS3-NEXT: bnez $1, .LBB5_2
; MIPS3-NEXT: dsrav $3, $4, $7
; MIPS3-NEXT: # %bb.1: # %entry
; MIPS3-NEXT: dsrlv $1, $5, $7
; MIPS3-NEXT: dsll $4, $4, 1
; MIPS3-NEXT: xori $2, $2, 63
; MIPS3-NEXT: dsllv $2, $4, $2
; MIPS3-NEXT: or $1, $2, $1
; MIPS3-NEXT: move $2, $3
; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: move $3, $1
; MIPS3-NEXT: .LBB5_2:
; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: dsra $2, $4, 63
;
; MIPS64-LABEL: ashr_i128:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: dsrlv $1, $5, $7
; MIPS64-NEXT: dsll $2, $4, 1
; MIPS64-NEXT: sll $5, $7, 0
; MIPS64-NEXT: xori $3, $5, 63
; MIPS64-NEXT: dsllv $2, $2, $3
; MIPS64-NEXT: or $3, $2, $1
; MIPS64-NEXT: dsrav $2, $4, $7
; MIPS64-NEXT: andi $1, $5, 64
; MIPS64-NEXT: movn $3, $2, $1
; MIPS64-NEXT: dsra $4, $4, 63
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: movn $2, $4, $1
;
; MIPS64R2-LABEL: ashr_i128:
; MIPS64R2: # %bb.0: # %entry
; MIPS64R2-NEXT: dsrlv $1, $5, $7
; MIPS64R2-NEXT: dsll $2, $4, 1
; MIPS64R2-NEXT: sll $5, $7, 0
; MIPS64R2-NEXT: xori $3, $5, 63
; MIPS64R2-NEXT: dsllv $2, $2, $3
; MIPS64R2-NEXT: or $3, $2, $1
; MIPS64R2-NEXT: dsrav $2, $4, $7
; MIPS64R2-NEXT: andi $1, $5, 64
; MIPS64R2-NEXT: movn $3, $2, $1
; MIPS64R2-NEXT: dsra $4, $4, 63
; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: movn $2, $4, $1
;
; MIPS64R6-LABEL: ashr_i128:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: dsrav $1, $4, $7
; MIPS64R6-NEXT: sll $3, $7, 0
; MIPS64R6-NEXT: andi $2, $3, 64
; MIPS64R6-NEXT: sll $6, $2, 0
; MIPS64R6-NEXT: seleqz $2, $1, $6
; MIPS64R6-NEXT: dsra $8, $4, 63
; MIPS64R6-NEXT: selnez $8, $8, $6
; MIPS64R6-NEXT: or $2, $8, $2
; MIPS64R6-NEXT: dsrlv $5, $5, $7
; MIPS64R6-NEXT: dsll $4, $4, 1
; MIPS64R6-NEXT: xori $3, $3, 63
; MIPS64R6-NEXT: dsllv $3, $4, $3
; MIPS64R6-NEXT: or $3, $3, $5
; MIPS64R6-NEXT: seleqz $3, $3, $6
; MIPS64R6-NEXT: selnez $1, $1, $6
; MIPS64R6-NEXT: jr $ra
; MIPS64R6-NEXT: or $3, $1, $3
;
; MMR3-LABEL: ashr_i128:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: addiusp -40
; MMR3-NEXT: .cfi_def_cfa_offset 40
; MMR3-NEXT: swp $16, 32($sp)
; MMR3-NEXT: .cfi_offset 17, -4
; MMR3-NEXT: .cfi_offset 16, -8
; MMR3-NEXT: sra $1, $4, 31
; MMR3-NEXT: swp $6, 24($sp)
; MMR3-NEXT: swp $4, 16($sp)
; MMR3-NEXT: sw $1, 12($sp)
; MMR3-NEXT: sw $1, 8($sp)
; MMR3-NEXT: sw $1, 4($sp)
; MMR3-NEXT: sw $1, 0($sp)
; MMR3-NEXT: addiur1sp $2, 0
; MMR3-NEXT: addiur2 $2, $2, 16
; MMR3-NEXT: lw $3, 68($sp)
; MMR3-NEXT: srl16 $4, $3, 3
; MMR3-NEXT: andi $4, $4, 12
; MMR3-NEXT: subu16 $5, $2, $4
; MMR3-NEXT: lwp $6, 4($5)
; MMR3-NEXT: andi16 $2, $3, 31
; MMR3-NEXT: srlv $16, $7, $2
; MMR3-NEXT: sll16 $3, $6, 1
; MMR3-NEXT: xori $1, $2, 31
; MMR3-NEXT: sllv $4, $3, $1
; MMR3-NEXT: srlv $6, $6, $2
; MMR3-NEXT: lw16 $17, 0($5)
; MMR3-NEXT: sll16 $3, $17, 1
; MMR3-NEXT: sllv $3, $3, $1
; MMR3-NEXT: or16 $3, $6
; MMR3-NEXT: or16 $4, $16
; MMR3-NEXT: lw16 $5, 12($5)
; MMR3-NEXT: srlv $6, $5, $2
; MMR3-NEXT: sll16 $5, $7, 1
; MMR3-NEXT: sllv $5, $5, $1
; MMR3-NEXT: or16 $5, $6
; MMR3-NEXT: srav $2, $17, $2
; MMR3-NEXT: lwp $16, 32($sp)
; MMR3-NEXT: addiusp 40
; MMR3-NEXT: jrc $ra
;
; MMR6-LABEL: ashr_i128:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: addiu $sp, $sp, -40
; MMR6-NEXT: .cfi_def_cfa_offset 40
; MMR6-NEXT: sw $16, 36($sp) # 4-byte Folded Spill
; MMR6-NEXT: .cfi_offset 16, -4
; MMR6-NEXT: sra $1, $4, 31
; MMR6-NEXT: sw $7, 28($sp)
; MMR6-NEXT: sw $6, 24($sp)
; MMR6-NEXT: sw $5, 20($sp)
; MMR6-NEXT: sw $4, 16($sp)
; MMR6-NEXT: sw $1, 12($sp)
; MMR6-NEXT: sw $1, 8($sp)
; MMR6-NEXT: sw $1, 4($sp)
; MMR6-NEXT: sw $1, 0($sp)
; MMR6-NEXT: addiu $2, $sp, 0
; MMR6-NEXT: addiur2 $2, $2, 16
; MMR6-NEXT: lw $3, 68($sp)
; MMR6-NEXT: srl16 $4, $3, 3
; MMR6-NEXT: andi $4, $4, 12
; MMR6-NEXT: subu16 $2, $2, $4
; MMR6-NEXT: lw16 $4, 4($2)
; MMR6-NEXT: lw16 $5, 8($2)
; MMR6-NEXT: andi16 $6, $3, 31
; MMR6-NEXT: srlv $1, $5, $6
; MMR6-NEXT: sll16 $3, $4, 1
; MMR6-NEXT: xori $7, $6, 31
; MMR6-NEXT: sllv $8, $3, $7
; MMR6-NEXT: srlv $3, $4, $6
; MMR6-NEXT: lw16 $16, 0($2)
; MMR6-NEXT: sll16 $4, $16, 1
; MMR6-NEXT: sllv $4, $4, $7
; MMR6-NEXT: or $3, $3, $4
; MMR6-NEXT: or $4, $1, $8
; MMR6-NEXT: lw16 $2, 12($2)
; MMR6-NEXT: srlv $1, $2, $6
; MMR6-NEXT: sll16 $2, $5, 1
; MMR6-NEXT: sllv $2, $2, $7
; MMR6-NEXT: or $5, $1, $2
; MMR6-NEXT: srav $2, $16, $6
; MMR6-NEXT: lw $16, 36($sp) # 4-byte Folded Reload
; MMR6-NEXT: addiu $sp, $sp, 40
; MMR6-NEXT: jrc $ra
entry:
%r = ashr i128 %a, %b
ret i128 %r
}
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