llvm/llvm/test/CodeGen/X86/apx/asm-constraint-1-jr.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: not llc -mtriple=x86_64 < %s >%t1 2>%t2
; RUN: FileCheck %s <%t1
; RUN: FileCheck %s <%t2 --check-prefix=ERR
; RUN: not llc -mattr=+egpr -mtriple=x86_64 < %s >%t1 2>%t2
; RUN: FileCheck %s <%t1
; RUN: FileCheck %s <%t2 --check-prefix=ERR
; RUN: not llc -mattr=+egpr,+inline-asm-use-gpr32 -mtriple=x86_64 < %s >%t1 2>%t2
; RUN: FileCheck %s <%t1
; RUN: FileCheck %s <%t2 --check-prefix=ERR

; CHECK: addq %r8, %rax
define void @constraint_jr_test() nounwind {
entry:
  %reg = alloca i64, align 8
  %0 = load i64, ptr %reg, align 8
  call void asm sideeffect "add $0, %rax", "^jr,~{rax},~{rbx},~{rbp},~{rcx},~{rdx},~{rdi},~{rsi},~{dirflag},~{fpsr},~{flags}"(i64 %0)
  ret void
}

; ERR: error: inline assembly requires more registers than available
define void @constraint_jr_test_err() nounwind {
entry:
  %reg = alloca i64, align 8
  %0 = load i64, ptr %reg, align 8
  call void asm sideeffect "add $0, %rax", "^jr,~{rax},~{rbx},~{rbp},~{rcx},~{rdx},~{rdi},~{rsi},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{dirflag},~{fpsr},~{flags}"(i64 %0)
  ret void
}