llvm/llvm/test/CodeGen/X86/xor-select-i1-combine.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
;RUN: llc < %s -O2 -mattr=+avx512f -mtriple=x86_64-unknown | FileCheck %s

@n = common dso_local global i32 0, align 4
@m = common dso_local global i32 0, align 4

define dso_local i32 @main(i8 %small) {
; CHECK-LABEL: main:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    testb $1, %dil
; CHECK-NEXT:    movl $m, %eax
; CHECK-NEXT:    movl $n, %ecx
; CHECK-NEXT:    cmoveq %rax, %rcx
; CHECK-NEXT:    movl (%rcx), %eax
; CHECK-NEXT:    retq
entry:
  %0 = and i8 %small, 1
  %cmp = icmp eq i8 %0, 0
  %m.n = select i1 %cmp, ptr @m, ptr @n
  %retval = load volatile i32, ptr %m.n, align 4
  ret i32 %retval
}


define dso_local i32 @main2(i8 %small) {
; CHECK-LABEL: main2:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    movl $m, %eax
; CHECK-NEXT:    movl $n, %ecx
; CHECK-NEXT:    testb $1, %dil
; CHECK-NEXT:    cmovneq %rax, %rcx
; CHECK-NEXT:    movl (%rcx), %eax
; CHECK-NEXT:    retq
entry:
  %0 = and i8 %small, 1
  %cmp = icmp eq i8 %0, 1
  %m.n = select i1 %cmp, ptr @m, ptr @n
  %retval = load volatile i32, ptr %m.n, align 4
  ret i32 %retval
}