llvm/llvm/test/CodeGen/X86/zext-inreg-1.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s

; These tests differ from the ones in zext-inreg-0.ll in that
; on x86-64 they do require and instructions.

; These should use movzbl instead of 'and 255'.
; This related to not having ZERO_EXTEND_REG node.

define i64 @l(i64 %d) nounwind  {
; CHECK-LABEL: l:
; CHECK:       # %bb.0:
; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT:    addl $1, %eax
; CHECK-NEXT:    adcl $0, %ecx
; CHECK-NEXT:    movzbl %cl, %edx
; CHECK-NEXT:    retl
        %e = add i64 %d, 1
        %retval = and i64 %e, 1099511627775
        ret i64 %retval
}
define i64 @m(i64 %d) nounwind  {
; CHECK-LABEL: m:
; CHECK:       # %bb.0:
; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT:    addl $1, %eax
; CHECK-NEXT:    adcl $0, %ecx
; CHECK-NEXT:    movzwl %cx, %edx
; CHECK-NEXT:    retl
        %e = add i64 %d, 1
        %retval = and i64 %e, 281474976710655
        ret i64 %retval
}