llvm/llvm/test/CodeGen/X86/2008-12-02-dagcombine-3.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s

target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.5"
; this should be rearranged to have two +s and one -
define i32 @test(ptr %a, ptr %L, ptr %P) nounwind {
; CHECK-LABEL: test:
; CHECK:       ## %bb.0: ## %entry
; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT:    addl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT:    subl %ecx, %eax
; CHECK-NEXT:    addl $-2, %eax
; CHECK-NEXT:    retl
entry:
        %0 = ptrtoint ptr %P to i32
        %1 = sub i32 -2, %0
        %2 = ptrtoint ptr %L to i32
        %3 = ptrtoint ptr %a to i32
	%4 = sub i32 %2, %3         	; <i32> [#uses=1]
	%5 = add i32 %1, %4		; <i32> [#uses=1]
	br label %return

return:		; preds = %bb3
	ret i32 %5
}