legalize-ext-x86-64.mir | Explore in Territory

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s

--- |
  define i64 @test_sext_i1(i8 %a) {
    %val = trunc i8 %a to i1
    %r = sext i1 %val to i64
    ret i64 %r
  }

  define i64 @test_sext_i8(i8 %val) {
    %r = sext i8 %val to i64
    ret i64 %r
  }

  define i64 @test_sext_i16(i16 %val) {
    %r = sext i16 %val to i64
    ret i64 %r
  }

  define i64 @test_sext_i32(i32 %val) {
    %r = sext i32 %val to i64
    ret i64 %r
  }

  define i64 @test_zext_i1(i8 %a) {
    %val = trunc i8 %a to i1
    %r = zext i1 %val to i64
    ret i64 %r
  }

  define i64 @test_zext_i8(i8 %val) {
    %r = zext i8 %val to i64
    ret i64 %r
  }

  define i64 @test_zext_i16(i16 %val) {
    %r = zext i16 %val to i64
    ret i64 %r
  }

  define i64 @test_zext_i32(i32 %val) {
    %r = zext i32 %val to i64
    ret i64 %r
  }

  define void @test_anyext_i1(i8 %a) {
    ret void
  }

  define void @test_anyext_i8(i8 %val) {
    ret void
  }

  define void @test_anyext_i16(i16 %val) {
    ret void
  }

  define void @test_anyext_i32(i32 %val) {
    ret void
  }


...
---
name:            test_sext_i1
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: test_sext_i1
    ; CHECK: liveins: $edi
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 63
    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]](s8)
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY [[C]](s8)
    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s8)
    ; CHECK-NEXT: $rax = COPY [[ASHR]](s64)
    ; CHECK-NEXT: RET 0, implicit $rax
    %0(s8) = COPY $dil
    %1(s1) = G_TRUNC %0(s8)
    %2(s64) = G_SEXT %1(s1)
    $rax = COPY %2(s64)
    RET 0, implicit $rax

...
---
name:            test_sext_i8
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: test_sext_i8
    ; CHECK: liveins: $edi
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s8)
    ; CHECK-NEXT: $rax = COPY [[SEXT]](s64)
    ; CHECK-NEXT: RET 0, implicit $rax
    %0(s8) = COPY $dil
    %1(s64) = G_SEXT %0(s8)
    $rax = COPY %1(s64)
    RET 0, implicit $rax

...
---
name:            test_sext_i16
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: test_sext_i16
    ; CHECK: liveins: $edi
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $di
    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s16)
    ; CHECK-NEXT: $rax = COPY [[SEXT]](s64)
    ; CHECK-NEXT: RET 0, implicit $rax
    %0(s16) = COPY $di
    %1(s64) = G_SEXT %0(s16)
    $rax = COPY %1(s64)
    RET 0, implicit $rax

...
---
name:            test_sext_i32
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: test_sext_i32
    ; CHECK: liveins: $edi
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s32)
    ; CHECK-NEXT: $rax = COPY [[SEXT]](s64)
    ; CHECK-NEXT: RET 0, implicit $rax
    %0(s32) = COPY $edi
    %1(s64) = G_SEXT %0(s32)
    $rax = COPY %1(s64)
    RET 0, implicit $rax

...
---
name:            test_zext_i1
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: test_zext_i1
    ; CHECK: liveins: $edi
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
    ; CHECK-NEXT: $rax = COPY [[AND]](s64)
    ; CHECK-NEXT: RET 0, implicit $rax
    %0(s8) = COPY $dil
    %1(s1) = G_TRUNC %0(s8)
    %2(s64) = G_ZEXT %1(s1)
    $rax = COPY %2(s64)
    RET 0, implicit $rax

...
---
name:            test_zext_i8
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: test_zext_i8
    ; CHECK: liveins: $edi
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s8)
    ; CHECK-NEXT: $rax = COPY [[ZEXT]](s64)
    ; CHECK-NEXT: RET 0, implicit $rax
    %0(s8) = COPY $dil
    %1(s64) = G_ZEXT %0(s8)
    $rax = COPY %1(s64)
    RET 0, implicit $rax

...
---
name:            test_zext_i16
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: test_zext_i16
    ; CHECK: liveins: $edi
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $di
    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s16)
    ; CHECK-NEXT: $rax = COPY [[ZEXT]](s64)
    ; CHECK-NEXT: RET 0, implicit $rax
    %0(s16) = COPY $di
    %1(s64) = G_ZEXT %0(s16)
    $rax = COPY %1(s64)
    RET 0, implicit $rax

...
---
name:            test_zext_i32
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: test_zext_i32
    ; CHECK: liveins: $edi
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
    ; CHECK-NEXT: $rax = COPY [[ZEXT]](s64)
    ; CHECK-NEXT: RET 0, implicit $rax
    %0(s32) = COPY $edi
    %1(s64) = G_ZEXT %0(s32)
    $rax = COPY %1(s64)
    RET 0, implicit $rax

...
---
name:            test_anyext_i1
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: test_anyext_i1
    ; CHECK: liveins: $edi
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
    ; CHECK-NEXT: $rax = COPY [[ANYEXT]](s64)
    ; CHECK-NEXT: RET 0, implicit $rax
    %0(s8) = COPY $dil
    %1(s1) = G_TRUNC %0(s8)
    %2(s64) = G_ANYEXT %1(s1)
    $rax = COPY %2(s64)
    RET 0, implicit $rax

...
---
name:            test_anyext_i8
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: test_anyext_i8
    ; CHECK: liveins: $edi
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
    ; CHECK-NEXT: $rax = COPY [[ANYEXT]](s64)
    ; CHECK-NEXT: RET 0, implicit $rax
    %0(s8) = COPY $dil
    %1(s64) = G_ANYEXT %0(s8)
    $rax = COPY %1(s64)
    RET 0, implicit $rax

...
---
name:            test_anyext_i16
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: test_anyext_i16
    ; CHECK: liveins: $edi
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $di
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s16)
    ; CHECK-NEXT: $rax = COPY [[ANYEXT]](s64)
    ; CHECK-NEXT: RET 0, implicit $rax
    %0(s16) = COPY $di
    %1(s64) = G_ANYEXT %0(s16)
    $rax = COPY %1(s64)
    RET 0, implicit $rax

...
---
name:            test_anyext_i32
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: test_anyext_i32
    ; CHECK: liveins: $edi
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
    ; CHECK-NEXT: $rax = COPY [[ANYEXT]](s64)
    ; CHECK-NEXT: RET 0, implicit $rax
    %0(s32) = COPY $edi
    %1(s64) = G_ANYEXT %0(s32)
    $rax = COPY %1(s64)
    RET 0, implicit $rax

...
llvm/llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
