llvm/llvm/test/CodeGen/X86/sar_fold.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s

define i32 @shl16sar15(i32 %a) #0 {
; CHECK-LABEL: shl16sar15:
; CHECK:       # %bb.0:
; CHECK-NEXT:    movswl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT:    addl %eax, %eax
; CHECK-NEXT:    retl
  %1 = shl i32 %a, 16
  %2 = ashr exact i32 %1, 15
  ret i32 %2
}

define i32 @shl16sar17(i32 %a) #0 {
; CHECK-LABEL: shl16sar17:
; CHECK:       # %bb.0:
; CHECK-NEXT:    movswl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT:    sarl %eax
; CHECK-NEXT:    retl
  %1 = shl i32 %a, 16
  %2 = ashr exact i32 %1, 17
  ret i32 %2
}

define i32 @shl24sar23(i32 %a) #0 {
; CHECK-LABEL: shl24sar23:
; CHECK:       # %bb.0:
; CHECK-NEXT:    movsbl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT:    addl %eax, %eax
; CHECK-NEXT:    retl
  %1 = shl i32 %a, 24
  %2 = ashr exact i32 %1, 23
  ret i32 %2
}

define i32 @shl24sar25(i32 %a) #0 {
; CHECK-LABEL: shl24sar25:
; CHECK:       # %bb.0:
; CHECK-NEXT:    movsbl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT:    sarl %eax
; CHECK-NEXT:    retl
  %1 = shl i32 %a, 24
  %2 = ashr exact i32 %1, 25
  ret i32 %2
}

define void @shl144sar48(ptr %p) #0 {
; CHECK-LABEL: shl144sar48:
; CHECK:       # %bb.0:
; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT:    movswl (%eax), %ecx
; CHECK-NEXT:    movl %ecx, %edx
; CHECK-NEXT:    sarl $31, %edx
; CHECK-NEXT:    shldl $2, %ecx, %edx
; CHECK-NEXT:    shll $2, %ecx
; CHECK-NEXT:    movl %ecx, 12(%eax)
; CHECK-NEXT:    movl %edx, 16(%eax)
; CHECK-NEXT:    movl $0, 8(%eax)
; CHECK-NEXT:    movl $0, 4(%eax)
; CHECK-NEXT:    movl $0, (%eax)
; CHECK-NEXT:    retl
  %a = load i160, ptr %p
  %1 = shl i160 %a, 144
  %2 = ashr exact i160 %1, 46
  store i160 %2, ptr %p
  ret void
}

define void @shl144sar2(ptr %p) #0 {
; CHECK-LABEL: shl144sar2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT:    movswl (%eax), %ecx
; CHECK-NEXT:    shll $14, %ecx
; CHECK-NEXT:    movl %ecx, 16(%eax)
; CHECK-NEXT:    movl $0, 8(%eax)
; CHECK-NEXT:    movl $0, 12(%eax)
; CHECK-NEXT:    movl $0, 4(%eax)
; CHECK-NEXT:    movl $0, (%eax)
; CHECK-NEXT:    retl
  %a = load i160, ptr %p
  %1 = shl i160 %a, 144
  %2 = ashr exact i160 %1, 2
  store i160 %2, ptr %p
  ret void
}