llvm/llvm/test/CodeGen/X86/sext-subreg.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
; rdar://7529457

define i64 @t(i64 %A, i64 %B, ptr %P, ptr%P2) nounwind {
; CHECK-LABEL: t:
; CHECK:       # %bb.0:
; CHECK-NEXT:    addq %rsi, %rdi
; CHECK-NEXT:    movl %edi, (%rdx)
; CHECK-NEXT:    movslq %edi, %rax
; CHECK-NEXT:    movq %rax, (%rcx)
; CHECK-NEXT:    movl %eax, (%rdx)
; CHECK-NEXT:    retq
  %C = add i64 %A, %B
  %D = trunc i64 %C to i32
  store volatile i32 %D, ptr %P
  %E = shl i64 %C, 32
  %F = ashr i64 %E, 32
  store volatile i64 %F, ptr%P2
  store volatile i32 %D, ptr %P
  ret i64 undef
}